參數(shù)資料
型號(hào)： IC42S16800L-8TIG
英文描述： 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述： 4（2）M中的x 8（16）位× 4銀行（128 - Mbit的）同步動(dòng)態(tài)RAM
文件頁(yè)數(shù)： 15/69頁(yè)
文件大?。?/td> 1118K
代理商： IC42S16800L-8TIG
IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004
15
CKE RELATED COMMAND TRUTH TABLE
(1)
CKE
n-1
Current State
Operation
n
CS
RAS
CAS
WE
Address
Self-Refresh (S.R.)
INVALID, CLK (n - 1)would exit S.R.
Self-Refresh Recovery
(2)
Self-Refresh Recovery
(2)
Illegal
Illegal
Maintain S.R.
Idle After t
RC
Idle After t
RC
Illegal
Illegal
Begin clock suspend next cycle
(5)
Begin clock suspend next cycle
(5)
Illegal
Illegal
Exit clock suspend next cycle
(2)
Maintain clock suspend
INVALID, CLK (n - 1) would exit P.D.
EXIT P.D.
→
Idle
(2)
Maintain power down mode
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Auto-Refresh
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Self-Refresh
(3)
Refer to operations in Operative Command Table
Power-Down
(3)
Refer to operations in Operative Command Table
Begin clock suspend next cycle
(4)
Exit clock suspend next cycle
Maintain clock suspend
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
X
H
H
H
H
L
H
H
H
H
L
L
L
L
H
L
X
H
L
H
H
H
H
H
L
L
L
L
L
X
H
L
H
L
X
H
L
L
L
X
H
L
L
L
H
L
L
L
X
X
X
X
X
H
L
L
L
L
H
L
L
L
L
X
X
X
X
X
X
X
H
H
L
X
X
H
H
L
X
H
H
L
X
X
X
X
X
X
H
L
L
L
X
H
L
L
L
X
X
X
X
X
X
X
H
L
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
X
X
H
L
L
X
X
H
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
X
X
—
—
—
X
Op - Code
—
—
—
X
Op - Code
X
X
X
X
X
Self-Refresh Recovery
Power-Down (P.D.)
Both Banks Idle
Any state
other than
listed above
Notes:
1.
2.
H : Hight level, L : low level, X : High or low level (Don’t care).
CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied
before any command other than EXIT.
Power down and Self refresh can be entered only from the both banks idle state.
Must be legal command as defined in Operative Command Table.
Illegal if t
SREX
is not satisfied.
3.
4.
5.
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