參數(shù)資料
型號: IC42S16800L-8TIG
英文描述: 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 4(2)M中的x 8(16)位× 4銀行(128 - Mbit的)同步動態(tài)RAM
文件頁數(shù): 27/69頁
文件大小: 1118K
代理商: IC42S16800L-8TIG
IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004
27
PRECHARGE TERMINATION
PRECHARGE TERMINATION in READ Cycle
During READ cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after t
RP
from the precharge command.
When
CAS
latency is 2, the read data will remain valid until one clock after the precharge command.
When
CAS
latency is 3, the read data will remain valid until two clocks after the precharge command.
Precharge Termination in READ Cycle
Burst lengh= X
CLK
Command
CA
S
l
a
t
e
n
cy
=
2
DQ
Hi-Z
Read
T0
T1
T2
T3
T4
T5
T6
T7
T8
PRE
ACT
DQ
Read
PRE
ACT
t
RP
CA
S
l
a
t
e
n
cy
=
3
Q0
Q3
Q2
Q1
Hi-Z
Q0
Q3
Q2
Q1
command
t
RP
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