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參數(shù)資料
| 型號(hào)： | IC42S16800L-8TIG |
| 英文描述： | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 4（2）M中的x 8（16）位× 4銀行（128 - Mbit的）同步動(dòng)態(tài)RAM |
| 文件頁(yè)數(shù)： | 20/69頁(yè) |
| 文件大?。?/td> | 1118K |
| 代理商： | IC42S16800L-8TIG |
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IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
20
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004
Precharge
The precharge command can be asserted anytime after t
RAS
(min.) is satisfied.
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters
the idle state after t
RP
(min.) is satisfied. The parameter t
RP
is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as
follows.
P
r
ec
h
a
r
g
e
E
Burst lengh=4
T7
CLK
Command
CA
S
l
a
t
e
n
cy
=
2
DQ
Command
CA
S
l
a
t
e
n
cy
=
3
DQ
(t
RAS
is satisfied)
Hi - Z
Q0
Q3
Q2
Q1
PRE
Q0
Q3
Q2
Q1
Read
Read
T0
T1
T2
T3
T4
T5
T6
PRE
Hi - Z
In order to write all data to the memory cell correctly, the asynchronous parameter t
DPL
must be satisfied. The t
DPL
(min.)
specification defines the earliest time that a precharge command can be asserted. The minimum number of clocks can be
calculated by dividing t
DPL
(min.) with the clock cycle time.
In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
CAS
latency
2
3
Read
-1
-2
Write
+ t
DPL
((min.)
+ t
DPL
((min.)
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| IC42S32200 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
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| IC42S32200/L-6BI | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S32200/L-6BIG | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
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