參數(shù)資料
型號： IC_SS
文件頁數(shù)： 6/36頁
文件大?。?/td> 480K
代理商： IC_SS
Pin Descriptions
(Continued)
TABLE II. ICSS1002 Pin Descriptions
(Continued)
Pin Name
Pin No
(V Pkg.)
Type
Function
D0–D7
33–40
I/O
Data Bus:
This is the parallel port data bus.
RD
42
T
Read:
This is the parallel port read control. Used with Chip Enable it allows the
parallel port to be read.
WR
43
T
Write:
This is the parallel port write control. Used with Chip Enable it allows the
parallel port to be written.
CE
44
T
Chip Enable:
This is the parallel port enable to read or write. It is active low.
DRV EN
45
O
Drive Enable:
This is the transmit enable signal used by the Analog chip to disable
the receiver mode and enable the transmitter mode
MTP4–MTP7
46–49
O
Test Points:
These output pins provide access to one of the filter outputs of the
detector integration bus
7F
50
O
Seventh Harmonic Overtone Cancellation Signal:
This is the seventh harmonic
overtone cancellation signal used to convert FSQWV to a sine wave in the Analog
chip D/A
5F
51
O
Fifth Harmonic Overtone Cancellation Signal:
This is the fifth harmonic overtone
cancellation signal used to convert FSQWV to a sine wave in the Analog chip D/A
3F
52
O
Third Harmonic Overtone Cancellation Signal:
This is the Third harmonic overtone
cancellation signal used to convert FSQWV to a sine wave in the Analog chip D/A
FSQWV
53
O
Square Wave Transmit Signal:
This is the Manchester-encoded frequency mixed
signal, ready for transmission to the power line
AD CLK
55
O
A/D Clock:
This is the clock for the Analog chip AID converter. It is used to latch the
AD output. It is the A/D sample rate. This is the CLK divided by 16. This output goes
HIGH while RESET is LOW.
AD3–AD0
56–59
T
Received Data:
These pins are the digital four bit bus from the Analog chip which
contains the ones complement A/D converted signal from the power line
C2–C0
61–63
O
Analog Gain Control:
These signals are used to set the gain of the Analog chip gain
controlled amplifier
Power on AC
64
O
Power on Reset RC Node:
This is the power on reset Resistor/Capacitor connect
point. An external RC network charges up to the gate threshold to release the RESET
signal. When this pin is LOW the RESET is active.
SEL4X8
66
T
Select 4X or 8X:
This is the select line used to set the digital filter clock sample rate
CLK
67
T
Clock:
This is the 16 MHz clock input
SEL TP
68
T
Select Test Points:
This signal selects which internal nodes are brought out on the
Test Point Bus and whether Raw Data is inverted or not
V
CC
4, 22, 41, 60
P
V
CC
:
These are positive voltage power supply pins to the part
GND
12, 17, 32,
54, 65
P
GND:
These are the negative (or 0V) power supply pins to the part
TABLE III. ICSS1003 Pin Descriptions
Pin Name
Pin No.
(V Pkg.)
Type
Function
GCO
1
Gain Control Amplifier Test Point:
A test point to monitor the gain of the gain amplifier
AGND
2
P
Analog Ground:
The ground reference pin for the gain control amplifier
V
CC
3
P
Digital Positive Power Supply Pin:
The V
CC
pin for the digital portion of the ASIC
C0–C2
4–6
I
Gain Control Amplifier Gain Setting:
These pins set the gain of the gain control amplifier.
These signals are generated by the digital ASIC.
ERR
7
O
A/D Overflow Signal:
This signal goes HIGH if the Analog signal from the gain control
amplifier to the Analog to Digital Converter is being clipped by the A/D converter
6
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