參數(shù)資料
型號(hào)： IC_SS
文件頁(yè)數(shù)： 13/36頁(yè)
文件大?。?/td> 480K
代理商： IC_SS
ICSS1002 AC Electrical Characteristics
(Continued)
All specifications guaranteed by simulation.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TPRDCLK
CLK Period
62.5
ns
TPWLCLK
CLK Pulse Width Low
25
31.25
37.5
ns
TPWHCLK
CLK Pulse Width High
25
31.25
37.5
ns
TPRD8
8 MHz Period
125
ns
TPWL8
8 MHz Pulse Width Low
62.5
ns
TPWH8
8 MHz Pulse Width High
62.5
ns
TPWK8R
Propagation Delay CLK to 8 MHz Going High
30
ns
TCLLK8L
Propagation Delay CLK to 8 MHz Going Low
30
ns
TPRDAD
AD CLK Period
1000
ns
TPWLAD
AD CLK Pulse Width Low
500
ns
TPWHAD
AD CLK Pulse Width High
500
ns
TCLKADR
Propagation Delay CLK to AD CLK Going High
40
ns
TCLKADL
Propagation Delay CLK to AD CLK Going Low
40
ns
TCKSIH
Propagation Delay CSD Bus Valid to SI Valid
30
ns
TSKSI
Propagation Delay SK Going Low to SI Next Value
30
ns
TPWHSK
Minimum Pulse Width High for SK
50
ns
TPWLSK
Minimum Pulse Width Low for SK
50
ns
TCDSIL
Propagation Delay CSD Bus Low to SI TRI-STATE
40
ns
TSUCDSK
Setup of CSD Bus Valid to SK Going High
20
ns
TSUSOSK
Setup of SO Valid Data to SK Going High
20
ns
THSOSK
Hold of SO Valid Data after SK Going High
20
ns
THCDSK
Hold of CSD Bus Valid after SK Going High
20
ns
TSUSTSK
Setup of SK Going High to STROBE Going High
50
ns
TCDRX
Propagation Delay CSD Bus Low to RXRDY High
30
ns
TSURXRD
Setup of RXRDY Going High to RD Going Low
20
ns
TSUSTRD
Setup of STROBE Going High to RD Going Low
20
ns
TRDRX
Propagation Delay RD High to RXRDY High
30
ns
TRDDBL
Propagation Delay RD Going Low to Data Bus Valid
30
ns
TRDDBH
Prop. Delay RD Going High to Data Bus TRI-STATE
30
ns
TPWRD
Minimum Pulse Width Low for RD
50
ns
TCDTX
Propagation Delay CSD Bus Low to TXRDY High
30
ns
TSUTXWR
Setup of TXRDY Going High to WR Going Low
20
ns
TSUDBWR
Setup of Data Bus Valid to WR Going Low
20
ns
TWRTX
Propagation Delay WR High to TXRDY Low
30
ns
THDBWR
Hold of Data Bus Valid after WR Going Low
20
ns
TPWWR
Minimum Pulse Width Low for WR
50
ns
13
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