參數(shù)資料
型號： IC_SS
文件頁數(shù)： 12/36頁
文件大小： 480K
代理商： IC_SS
ICSS1002 AC Electrical Characteristics
The AC Electrical Characteristics for the ICSS1002 are not measured. They are guaranteed by design, unless otherwise noted.
The CLK input should be a 16 MHz signal with a period of 62.5 ns and with t
PWLCLK
and t
PWHCLK
of 31.25 ns 6.25 ns. This is
equivalent to requiring a 50% 10% duty cycle on the CLK input. See Figure 2.
TL/DD/11727–6
FIGURE 1. Clock (CLK) Input
8 MHz Output
With a 16 MHz input on CLK, the 8 MHz output will be an 8 MHz square wave with a t
PRD8
of 125 ns and with t
PWH8
and t
PWL8
of 62.5 ns. The 8 MHz signal will transition on rising edges of the CLK signal.
TL/DD/11727–7
FIGURE 2. 8 MHz Output
AD CLK Output
With a 16 MHz input on CLK, the AD CLK output will be a 1.0 MHz square wave with a t
PRDAD
of 1.0 ms and with t
PWHAD
and
t
PWLAD
of 0.5 ms. The AD CLK signal will transition on rising edges of the CLK signal.
TL/DD/11727–8
FIGURE 3. AD CLK Output
12
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