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| 型號(hào)： | IBMN364404CT3C-75A |
| 英文描述： | x4 SDRAM |
| 中文描述： | x4內(nèi)存 |
| 文件頁數(shù)： | 31/71頁 |
| 文件大?。?/td> | 1251K |
| 代理商： | IBMN364404CT3C-75A |
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IBMN364164
IBMN364404
IBMN364804
64Mb Synchronous DRAM - Die Revision C
19L3265.E35856B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 31 of 71
Command Truth Table
(See note 1)
Function
Device State
CKE
CS
RAS
CAS
WE
DQM
A12,
A13
A10
A11, A9-
A0
Notes
Previous
Cycle
Current
Cycle
Mode Register Set
Idle
H
X
L
L
L
L
X
OP Code
Auto (CBR) Refresh
Entry Self Refresh
Idle
Idle
H
H
H
L
L
L
L
L
L
L
H
H
X
X
X
X
X
X
X
X
Exit Self Refresh
Idle (Self-
Refresh)
L
H
H
X
X
X
X
X
X
X
L
H
H
H
Single Bank Precharge
See Current
State Table
H
X
L
L
H
L
X
BS
L
X
2
Precharge all Banks
See Current
State Table
H
X
L
L
H
L
X
X
H
X
Bank Activate
Idle
H
X
L
L
H
H
X
BS
Row Address
2
Write
Active
H
X
L
H
L
L
X
BS
L
Column
2
Write with Auto-Precharge Active
H
X
L
H
L
L
X
BS
H
Column
2
Read
Active
H
X
L
H
L
H
X
BS
L
Column
2
Read with Auto-Precharge Active
H
X
L
H
L
H
X
BS
H
Column
2
Burst Termination
Active
H
X
L
H
H
L
X
X
X
X
3, 8
No Operation
Device Deselect
Any
Any
H
H
X
X
L
H
H
X
H
X
H
X
X
X
X
X
X
X
X
X
Clock Suspend Mode
Entry
Active
H
L
X
X
X
X
X
X
X
X
4
Clock Suspend Mode Exit
Active
L
H
X
X
X
X
X
X
X
X
Data Write/Output Enable
Active
H
X
X
X
X
X
L
X
X
X
5
Data Mask/Output Disable Active
H
X
X
X
X
X
H
X
X
X
Power Down Mode Entry
Idle/Active
H
L
H
X
X
X
X
X
X
X
6, 7
L
H
H
X
H
X
H
X
Power Down Mode Exit
Any (Power
Down)
L
H
X
X
X
X
6, 7
L
H
H
H
1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Refer
to the Current State Truth Table.
2. Bank Select (BS0, BS1): BS0, BS1 = 0,0 selects bank 0; BS0, BS1 = 0,1 selects bank 1; BS0, BS1 = 1,0 selects bank 2; BS0, BS1
= 1,1 selects bank 3.
3. During a Burst Write cycle there is a zero clock delay; for a Burst Read cycle the delay is equal to the CAS latency.
4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data
Read and Write operations. One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock tim-
ing the data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for
Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency).
6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the
device state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device
can’t remain in this mode longer than the Refresh period (t
REF
) of the device. One clock delay is required for mode entry and exit.
7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.
8. Device state is full page burst operation. Use of this command to terminate other burst length operations is illegal.
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