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| 型號(hào)： | IBMN364404CT3C-75A |
| 英文描述： | x4 SDRAM |
| 中文描述： | x4內(nèi)存 |
| 文件頁數(shù)： | 22/71頁 |
| 文件大小： | 1251K |
| 代理商： | IBMN364404CT3C-75A |
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IBMN364164
IBMN364404
64Mb Synchronous DRAM - Die Revision C
IBMN364804
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 22 of 71
19L3265.E35856B
1/01
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank
undergoing auto-precharge cannot be reactivated until t
DAL
, Data-in to Active delay, is satisfied.
Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command
to the same bank. It can be interrupted by a Read or Write Command to a different bank, however. The pre-
charge function will be initiated by the new command. After the Data-in to Active, delay, t
DAL
, is satisfied the
bank may be reactivated.
Burst Write with Auto-Precharge
Burst Write with Auto-Precharge Interrupted by Write
DIN A
0
COMMAND
NOP
NOP
NOP
NOP
Auto-Precharge
DIN A
1
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
*
DIN A
0
DIN A
1
t
CK2,
DQs
CAS latency = 2
t
CK3,
DQs
CAS latency = 3
NOP
NOP
NOP
*
Number of clocks required depends on clock cycle
time and speed sort.
Bank can be reactivated at completion of t
DAL
.
t
DAL
t
DAL
*
(Burst Length = 2, CAS Latency = 2, 3)
See the Clock Frequency and Latency table.
DIN A
0
COMMAND
NOP
NOP
NOP
*
Auto-Precharge
DIN A
1
t
DAL
CLK
T0
T1
T2
T3
T4
T5
NOP
t
CK3,
DQs
CAS latency = 3
WRITE B
DIN B
0
DIN B
1
DIN B
2
DIN B
3
T6
T7
T8
NOP
NOP
NOP
*
Number of clocks required depends on clock cycle
time and speed sort.
Bank can be reactivated at completion of t
DAL
.
(Burst Length = 4, CAS Latency = 3)
See the Clock Frequency and Latency table.
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