參數(shù)資料
型號: HYS72D256520GR
廠商: INFINEON TECHNOLOGIES AG
英文描述: 184 Pin Registered Double Data Rate SDRAM Modules
中文描述: 184針注冊雙倍數(shù)據(jù)速率SDRAM模塊
文件頁數(shù): 8/25頁
文件大?。?/td> 638K
代理商: HYS72D256520GR
HYS72D256520GR-7-A
Registered Double Data Rate SDRAM Modules
Pin Configuration
Data Sheet
8
Rev. 1.02, 2003-12
10282003-P6EY-RWQ2
2
Pin Configuration
Table 3
Symbol
A0 - A11,A12
Pin Definitions and Functions
Type
Function
Address Inputs
(A12 for 256Mb & 512Mb based modules)
Bank Selects
Data Input/Output
Check Bits (
×
72 organization only)
Row Address Strobe
Column Address Strobe
Read/Write Input
Clock Enable
SDRAM low data strobes
Differential Clock Input
SDRAM low data mask/
high data strobes
Chip Selects
Power (+2.5 V)
Ground
I/O Driver power supply
VDD Indentification flag
EEPROM power supply
I/O reference supply
Serial bus clock
Serial bus data line
slave address select
no connect
don’t use
Reset pin (forces register inputs low)
1)
BA0, BA1
DQ0 - DQ63
CB0 - CB7
RAS
CAS
WE
CKE0, CKE1
DQS0 - DQS8
CK0, CK0
DQS9 - DQS17
CS0 - CS1
V
DD
V
SS
V
DDQ
V
DDID
V
DDSPD
V
REF
SCL
SDA
SA0 - SA2
NC
DU
RESET
1) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the Application Note at
the end of this datasheet
Table 4
Density
Address Format
Organization Memory
Ranks
2
SDRAMs
# of
SDRAMs
36
(stacked)
# of row/bank/
column bits
13/2/12
Refresh
Period Interval
2 GB
256M x 72
(512Mb)
128M
×
4
8k
64 ms
7.8
μ
s
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