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參數(shù)資料
| 型號： | HYS72D256520GR |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 184 Pin Registered Double Data Rate SDRAM Modules |
| 中文描述： | 184針注冊雙倍數(shù)據(jù)速率SDRAM模塊 |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 638K |
| 代理商： | HYS72D256520GR |
HYS72D256520GR-7-A
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Data Sheet
13
Rev. 1.02, 2003-12
10282003-P6EY-RWQ2
Output Leakage Current
I
OZ
–5
5
μ
A
DQs are disabled;
0 V
≤
V
OUT
≤
V
DDQ
V
OUT
= 1.95 V
Output High Current,
Normal Strength Driver
Output Low
Current, Normal Strength
Driver
I
OH
—
–16.2
mA
I
OL
16.2
—
mA
V
OUT
= 0.35 V
1) 0
°
C
≤
T
A
≤
70
°
C
2) Under all conditions,
V
DDQ
must be less than or equal to
V
DD
.
3) Peak to peak AC noise on
V
REF
may not exceed ± 2%
V
REF (DC)
.
V
REF
is also expected to track noise variations in
V
DDQ
.
4)
V
TT
is not applied directly to the device.
V
TT
is a system supply for signal termination resistors, is expected to be set equal
to
V
REF
, and must track variations in the DC level of
V
REF
.
5)
V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
6) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
7) Inputs are not recognized as valid until
V
REF
stabilizes.
8) Values are shown per DDR SDRAM component
Table 8
Parameter
Operating Current:
one bank; active/ precharge;
t
RC
=
t
RCMIN
;
t
CK
=
t
CKMIN
;
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once
every two clock cycles.
Operating Current:
one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current:
all banks idle; power-down mode; CKE
≤
V
ILMAX
;
t
CK
=
t
CKMIN
Precharge Floating Standby Current:
CS
≥
V
IHMIN
, all banks idle;
CKE
≥
V
IHMIN
;
t
CK
=
t
CKMIN
, address and other control inputs changing once per clock cycle,
V
IN
=
V
REF
for DQ, DQS and DM.
Precharge Quiet Standby Current:
CS
≥
V
IHMIN
, all banks idle; CKE
≥
V
IHMIN
;
t
CK
=
t
CKMIN
, address and other control inputs stable
at
≥
V
IHMIN
or
≤
V
ILMAX
;
V
IN
=
V
REF
for DQ, DQS and DM.
Active Power-Down Standby Current:
one bank active; power-down mode;
CKE
≤
V
ILMAX
;
t
CK
=
t
CKMIN
;
V
IN
=
V
REF
for DQ, DQS and DM.
Active Standby Current:
one bank active; CS
≥
V
IHMIN
; CKE
≥
V
IHMIN
;
t
RC
=
t
RASMAX
;
t
CK
=
t
CKMIN
; DQ,
DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock
cycle.
Operating Current:
one bank active; Burst = 2; reads; continuous burst; address and control inputs
changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200
and DDR266A, CL = 3 for DDR333;
t
CK
=
t
CKMIN
;
I
OUT
= 0 mA
Operating Current:
one bank active; Burst = 2; writes; continuous burst; address and control inputs
changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200
and DDR266A, CL = 3 for DDR333;
t
CK
=
t
CKMIN
I
DD
Conditions
Symbol
I
DD0
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P
I
DD3N
I
DD4R
I
DD4W
Table 7
Parameter
Electrical Characteristics and DC Operating Conditions
(cont’d)
Symbol
Min.
Values
Typ.
Unit Note/Test Condition
1)
Max.
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