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參數(shù)資料
| 型號： | HYS72D256520GR |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 184 Pin Registered Double Data Rate SDRAM Modules |
| 中文描述： | 184針注冊雙倍數(shù)據(jù)速率SDRAM模塊 |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 638K |
| 代理商： | HYS72D256520GR |
HYS72D256520GR-7-A
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Data Sheet
15
Rev. 1.02, 2003-12
10282003-P6EY-RWQ2
Table 10
Electrical Characteristics & AC Timing for DDR components
(for reference only)
70
°
C
≤
T
A
≤
70
°
C;
V
DDQ
= 2.5 V
±
0.2 V;
V
DD
= 2.5 V
±
0.2 V
Parameter
Symbol
DDR266A
–
7
min.
–0.75
–0.75
0.45
0.45
min. (
t
CL
,
t
CH
)
7
7.5
0.5
0.5
2.2
1.75
Unit
Notes
max.
+0.75
+0.75
0.55
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
t
AC
t
DQSCK
t
CH
t
CL
t
HP
t
CK
t
CK
t
DH
t
DS
t
IPW
t
DIPW
ns
ns
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
1) to 4)
1) to 4)
1) to 4)
1) to 4)
1) to 4)
CL = 2.5
CL = 2.0
12
12
–
–
–
–
1) to 4)
1) to 4)
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width (each input)
DQ and DM input pulse width
(each input)
Data-out high-impedence time from CK/CK
Data-out low-impedence time from CK/CK
Write command to 1st DQS latching transition
DQS-DQ skew (for DQS & associated DQ signals)
Data hold skew factor
Data Output hold time from DQS
DQS input low (high) pulse width
(write cycle)
DQS falling edge to CK setup time (write cycle)
DQS falling edge hold time from CK (write cycle)
Mode register set command cycle time
Write preamble setup time
Write postamble
Write preamble
Address and control input setup time
1) to 4)
1) to 4)
1)10)
1) to 4)11)
t
HZ
t
LZ
t
DQSS
t
DQSQ
t
QHS
t
QH
t
DQSL,H
–
–0.8
0.75
–
–
(
t
HP
–
t
QHS
)
0.35
+0.8
+0.8
1.25
+0.5
+0.75
ns
ns
t
CK
ns
ns
ns
t
CK
1) to 4)5)
1) to 4)5)
1) to 4)
1) to 4)
1) to 4)
1) to 4)
–
1) to 4)
t
DSS
t
DSH
t
MRD
t
WPRES
t
WPST
t
WPRE
0.2
0.2
14
0
0.40
0.25
0.9
1.0
–
–
–
–
0.60
–
–
–
t
CK
t
CK
ns
ns
t
CK
1) to 4)
1) to 4)
1) to 4)
1) to 4)7)
1) to 4)6)
1) to 4)
fast slew rate
t
IS
slow slew
rate
fast slew rate
t
IH
slow slew
rate
ns
ns
2) to 4)10)11)
Address and control input hold time
0.9
1.0
–
–
ns
ns
Read preamble
Read postamble
Active to Precharge command
t
RPRES
t
RPST
t
RAS
0.9
0.40
45
1.1
0.60
120,00
0
–
–
t
CK
t
CK
ns
1) to 4)
3)
1) to 4)
4)
1) to 4)
5)
Active to Active/Auto-refresh command period
Auto-refresh to Active/Auto-refresh
command period
t
RC
t
RFC
65
75
ns
ns
1) to 4)
6)
1) to 4)
7)
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