參數(shù)資料
型號: HYB25R128160C-840
英文描述: RAMBUS DRAM
中文描述: Rambus的內(nèi)存
文件頁數(shù): 37/76頁
文件大?。?/td> 1218K
代理商: HYB25R128160C-840
2002-05-06
Page 37 of 76
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS
Latency = 2; Burst Length = 8)
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 3 data elements are written.
2 subsequent elements of data in are applied in the programmed order following DI a-b.
t
W
TR
is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)
The Read command masks the last 2 data elements in the burst.
A10 is Low with the
W
rite command (Auto Precharge is disabled).
The Read and
W
rite commands are not necessarily to the same bank.
1 = This bit is correctly written into the memory array if DM is low.
2 = These bits are incorrectly written into the memory array if DM is low.
Don’t Care
T1
T2
T3
T4
T5
T6
N
OP
N
OP
N
OP
Read
W
rite
N
OP
CK
CK
Command
Address
BAa, COL b
BAa, COL n
t
W
TR
DI a-b
DQS
DQ
CL = 2
t
DQSS
(min)
DM
1
2
2
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