參數(shù)資料
型號: HYB25L128160AC
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES
中文描述: 128 - Mbit同步低功率DRAM在CHIPSIZE套票
文件頁數(shù): 6/50頁
文件大?。?/td> 980K
代理商: HYB25L128160AC
HYB/E 25L128160AC
128-MBit Mobile-RAM
INFINEON Technologies
6
2003-02
LDQM
UDQM,
Input
Pulse
Active
High
The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQMx
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
LDQM and UDQM controls the lower and upper bytes in
x16 SDRAM.
V
DD
V
SS
Supply
Power and ground for the input buffers and the core logic.
V
DDQ
V
SSQ
Supply
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
Pin
Type
Signal Polarity Function
相關(guān)PDF資料
PDF描述
HYB25L128160AC-8 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES
HYE25L128160AC-8 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES
HYB25L128160AC-7.5 HEX DIE SET,.052/.068/.100/.21
HYE25L128160AC-7.5 HEX DIE SET,.052/.068/.178/.25
HYE25L128160AC-75 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES
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