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參數(shù)資料
| 型號： | HYB25L128160AC |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES |
| 中文描述： | 128 - Mbit同步低功率DRAM在CHIPSIZE套票 |
| 文件頁數(shù)： | 11/50頁 |
| 文件大?。?/td> | 980K |
| 代理商： | HYB25L128160AC |
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HYB/E 25L128160AC
128-MBit Mobile-RAM
INFINEON Technologies
11
2003-02
Similar to the page mode of conventional DRAM
’
s, burst read or write accesses on any column
address are possible once the RAS cycle latches the sense amplifiers. The maximum
W
RAS
or the
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
When the previous burst is interrupted, the remaining addresses are overridden by the new address
with the full burst length. An interrupt which accompanies an operation change from a read to a write
is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations are
possible. With the programmed burst length, alternate access and precharge operations on two or
more banks can realize fast serial data access modes among many different pages. Once two or
more banks are activated, column to column interleave operation can be performed between
different pages. When the partial array activation is set, data will get lost when self-refresh is used
in all non activated banks.
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Mobile-RAM has two refresh modes, Auto Refresh and Self Refresh.
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Auto Refresh is similar to the CAS -before-RAS refresh of earlier DRAMs. All banks must be
precharged before applying any refresh mode. An on-chip address counter increments the word
and the bank addresses. No bank information is required for both refresh modes.
Burst Length and Sequence
Burst
Length
Starting
Address
(A2 A1 A0)
Sequential Burst
Addressing
(decimal)
Interleave Burst
Addressing
(decimal)
2
xx0
xx1
0, 1
1, 0
0, 1
1, 0
4
x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
8
000
001
010
011
100
101
110
111
0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0
2 3 4 5 6 7 0 1
3 4 5 6 7 0 1 2
4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4
6 7 0 1 2 3 4 5
7 0 1 2 3 4 5 6
0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1 0
Full Page
nnn
Cn, Cn+1, Cn+2
not supported
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25L128160AC-8 | 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES |
| HYE25L128160AC-8 | 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES |
| HYB25L128160AC-7.5 | HEX DIE SET,.052/.068/.100/.21 |
| HYE25L128160AC-7.5 | HEX DIE SET,.052/.068/.178/.25 |
| HYE25L128160AC-75 | 128-MBIT SYNCHRONOUS LOW-POWER DRAM IN CHIPSIZE PACKAGES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25L256160AC-7.5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB25L512160AC-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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