參數(shù)資料
型號(hào)： HYB25D512400AR-7
英文描述： ?512Mb (stacked 256Mb) ?
中文描述： ？的512Mb（堆疊256Mb的）？
文件頁(yè)數(shù)： 57/76頁(yè)
文件大?。?/td> 1218K
代理商： HYB25D512400AR-7
2002-05-06
Page 57 of 76
HYB25D128400/800/160AT(L)
128-Mbit Double Data Rate SDRAM
IDD Current Measurement Conditions
IDD1 : Operating current : One bank operation
1. Only one bank is accessed with t
RC(min)
, Burst Mode, Address and Control inputs on
N
OP edge are changing once
per clock cycle. l
out
= 0 mA
2. Timing patterns
-
DDR200
(100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRCD = 2
*
tCK, tRAS = 5
*
tCK
Setup: A0
N
R0
N N
P0
N
Read : A0
N
R0
N N
P0
N
- repeat the same timing with random address changing
50
%
of data changing at every burst
-
DDR266A
(133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRCD = 3
*
tCK, tRC =
9 *
tCK, tRAS = 5
*
tCK
Setup: A0
N N
R0
N
P0
N N N
Read : A0
N N
R0
N
P0
N NN
- repeat the same timing with random address changing
50
%
of data changing at every burst
-
DDR333
(166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRCD = 3
*
tCK, tRC =
9 *
tCK, tRAS = 5
*
tCK
Setup: A0
N N
R0
N
P0
N N N
Read : A0
N N
R0
N
P0
N N N
- repeat the same timing with random address changing
50
%
of data changing at every burst
3.Legend : A=Activate, R=Read,
W
=
W
rite, P=Precharge,
N
=
N
OP
IDD7 : Operating current: Four bank operation
1. Four banks are being interleaved with t
RC(min)
, Burst Mode, Address and Control inputs on
N
OP edge are not
changing. l
out
= 0 mA
2. Timing patterns
-
DDR200
(100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRRD = 2
*
tCK, tRCD= 3
*
tCK, Read with autoprecharge
Setup: A0
N
A1 R0 A2 R1 A3 R2
Read : A0 R3 A1 R0 A2 R1 A3 R2- repeat the same timing with random address changing
50
%
of data changing at every burst
-
DDR266A
(133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRRD = 2
*
tCK, tRCD = 3
*
tCK
Setup: A0
N
A1 R0 A2 R1 A3 R2
N
R3
Read : A0
N
A1 R0 A2 R1 A3 R2
N
R3 - repeat the same timing with random address changing
50
%
of data changing at every burst
-
DDR333
(166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRRD = 2
*
tCK, tRCD = 3
*
tCK
Setup: A0
N
A1 R0 A2 R1 A3 R2
N
R3
Read : A0
N
A1 R0 A2 R1 A3 R2
N
R3 - repeat the same timing with random address changing
50
%
of data changing at every burst
3.Legend : A=Activate, R=Read,
W
=
W
rite, P=Precharge,
N
=
N
OP
相關(guān)PDF資料
PDF描述
HYB25D512400AT-8 ?512Mb (128Mx4) DDR200 (2-2-2) ?
HYB25D512800AT-6 ?512Mb (64Mx8) DDR333 (2.5-3-3)?
HYB25D512800AT-7 ?512Mb (64Mx8) DDR266A (2-3-3)?
HYB25D512800AT-8 ?512Mb (64Mx8) DDR200 (2-2-2)?
HYB25M128160C-653 RAMBUS DRAM
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參數(shù)描述
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