參數(shù)資料
型號: HY5PS12821F-4
廠商: Hynix Semiconductor Inc.
英文描述: 512Mb DDR2 SDRAM
中文描述: 512Mb DDR2 SDRAM芯片
文件頁數(shù): 33/35頁
文件大?。?/td> 624K
代理商: HY5PS12821F-4
Rev. 1.0 / Feb. 2005
33
1
HY5PS12421(L)F
HY5PS12821(L)F
HY5PS121621(L)F
these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two
20. Input waveform timing with differential data strobe enabled MR[bit10] =0, is referenced from the input signal cross-
ing at the V
IH
(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at
the V
IL
(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test.
21. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal cross-
ing at the V
IH
(dc) level to the differential data strobe crosspoint for a rising signal and V
IL
(dc) to the differential data
strobe crosspoint for a falling signal applied to the device under test.
22. Input waveform timing is referenced from the input signal crossing at the V
IH
(ac) level for a rising signal and V
IL
(ac)
for a falling signal applied to the device under test.
23. Input waveform timing is referenced from the input signal crossing at the V
IL
(dc) level for a rising signal and V
IH
(dc)
for a falling signal applied to the device under test.
tHZ , tRPST end point = 2*T1-T2
tLZ , tRPRE begin point = 2*T1-T2
VOH + xmV
VOH + 2xmV
VOL + 1xmV
VOL + 2xmV
tHZ
tRPST end point
VTT + 2xmV
VTT + xmV
VTT -xmV
VTT - 2xmV
tHZ
tRPRE begin point
DQS
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
tDH
tDS
DQS
V
REF
(dc)
V
IL(dc)
max
V
SS
V
IL(ac)
max
tDH
tDS
Differential Input waveform timing
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HY5PS121621F 512Mb DDR2 SDRAM
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相關代理商/技術參數(shù)
參數(shù)描述
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HY5PS12821LF 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM