參數(shù)資料
型號(hào)： HY5PS12821F-4
廠商： Hynix Semiconductor Inc.
英文描述： 512Mb DDR2 SDRAM
中文描述： 512Mb DDR2 SDRAM芯片
文件頁數(shù)： 31/35頁
文件大小： 624K
代理商： HY5PS12821F-4
Rev. 1.0 / Feb. 2005
31
1
HY5PS12421(L)F
HY5PS12821(L)F
HY5PS121621(L)F
9. tIS and tIH (input setup and hold) derating
1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the datasheet value
to the derating value listed in above Table.
Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
REF
(dc) and
the first crossing of V
IH
(ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as the slew rate between the
last crossing of V
REF
(dc) and the first crossing of V
IL
(ac)max. If the actual signal is always earlier than the nominal
slew rate for line between shaded ‘V
REF
(dc) to ac region’, use nominal slew rate for derating value(see fig a.) If the
actual signal is later than the nominal slew rate line anywhere between shaded ‘V
REF
(dc) to ac region’, the slew rate of
a tangent line to the actual signal from the ac level to dc level is used for derating value(see Fig b.)
Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and
the first crossing of V
REF
(dc). Hold(tIH) nominal slew rate for a falling signal is defined as the slew rate between the
last crossing of V
REF
(dc). If the actual signal signal is always later than the nominal slew rate line between shaded ‘dc
to V
REF
(dc) region’, use nominal slew rate for derating value(see Fig.c) If the actual signal is earlier than the nominal
slew rate line anywhere between shaded ‘dc to V
REF
(dc) region’, the slew rate of a tangent line to the actual signal
from the dc level to V
REF
(dc) level is used for derating value(see Fig d.)
Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached V
IH/IL
(ac) at
the time of the rising clock transition) a valid input signal is still required to complete the transition and reach V
IH/IL
(ac).
For slew rates in between the values listed in table, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
△
tIS
△
tIH
△
tIS
△
tIH
△
tIS
△
tIH
Units
Notes
4.0
+187
+94
TBD
TBD
TBD
TBD
ps
1
3.5
+179
+89
TBD
TBD
TBD
TBD
ps
1
3.0
+167
+83
TBD
TBD
TBD
TBD
ps
1
2.5
+150
+75
TBD
TBD
TBD
TBD
ps
1
2.0
+125
+45
TBD
TBD
TBD
TBD
ps
1
1.5
+83
+21
TBD
TBD
TBD
TBD
ps
1
1.0
+0
0
TBD
TBD
TBD
TBD
ps
1
0.9
-11
-14
TBD
TBD
TBD
TBD
ps
1
0.8
-25
-31
TBD
TBD
TBD
TBD
ps
1
0.7
-43
-54
TBD
TBD
TBD
TBD
ps
1
0.6
-67
-83
TBD
TBD
TBD
TBD
ps
1
0.5
-100
-125
TBD
TBD
TBD
TBD
ps
1
0.4
-150
-188
TBD
TBD
TBD
TBD
ps
1
0.3
-223
-292
TBD
TBD
TBD
TBD
ps
1
0.25
-250
-375
TBD
TBD
TBD
TBD
ps
1
0.2
-500
-500
TBD
TBD
TBD
TBD
ps
1
0.15
-750
-708
TBD
TBD
TBD
TBD
ps
1
0.1
-1250
-1125
TBD
TBD
TBD
TBD
ps
1
tIS, tIH Derating Values
Differential Slew Rate
Command /
Address
Slew
rate(V/ns)
2.0 V/ns
CK, CK
1.5 V/ns
1.0 V/ns
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