- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385428 > HY5DV641622AT-33 (HYNIX SEMICONDUCTOR INC) 64M(4Mx16) DDR SDRAM PDF資料下載
參數(shù)資料
| 型號： | HY5DV641622AT-33 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 64M(4Mx16) DDR SDRAM |
| 中文描述： | 4M X 16 DDR DRAM, 0.5 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數(shù)： | 3/27頁 |
| 文件大小： | 276K |
| 代理商： | HY5DV641622AT-33 |
第1頁第2頁當前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
DESCRIPTION
The Hynix HY5DV641622 is a 67,108,864-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the
point-to-point applications which requires high bandwidth.
The Hynix 4Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
3.3V for V
DD
and 2.5V for V
DDQ
power supply
All inputs and outputs are compatible with SSTL_2
interface
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has 2 bytewide data strobes (LDQS,
UDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Write mask byte controls by LDM and UDM
Programmable /CAS Latency 3 / 4 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal 4 bank operations with single pulsed /RAS
tRAS Lock-Out function supported
Auto refresh and self refresh supported
4096 refresh cycles / 64ms
Full, Half and Matched Impedance(Weak) strength
driver option controlled by EMRS
ORDERING INFORMATION
Part No.
Power Supply
Clock
Frequency
Max Data Rate
interface
Package
HY5DV641622AT-33
V
DD
=3.3V
V
DDQ
=2.5V
300MHz
600Mbps/pin
SSTL_2
400mil 66pin
TSOP-II
HY5DV641622AT-36
275MHz
550Mbps/pin
HY5DV641622AT-4
250MHz
500Mbps/pin
HY5DV641622AT-5
200MHz
400Mbps/pin
HY5DV641622AT
Rev. 0.7/May. 02 3
相關PDF資料 |
PDF描述 |
|---|---|
| HY5DV641622AT-36 | 64M(4Mx16) DDR SDRAM |
| HY5DV641622AT-4 | 64M(4Mx16) DDR SDRAM |
| HY5DV641622AT-5 | 64M(4Mx16) DDR SDRAM |
| HY5PS121621FP | 512Mb DDR2 SDRAM |
| HY5PS121621FP-X | 512Mb DDR2 SDRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DV641622AT-36 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:64M(4Mx16) DDR SDRAM |
| HY5DV641622AT-4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:64M(4Mx16) DDR SDRAM |
| HY5DV641622AT-5 | 制造商:SK Hynix Inc 功能描述: |
| HY5DV651622TC-G55 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
| HY5DV651622TC-G6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。