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參數(shù)資料
| 型號： | HY5DU12422ALT-X |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 512Mb DDR SDRAM |
| 中文描述： | 產(chǎn)品512Mb DDR SDRAM |
| 文件頁數(shù)： | 31/33頁 |
| 文件大小： | 379K |
| 代理商： | HY5DU12422ALT-X |
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Rev. 0.0/Feb. 2003 31
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
5.
CK, /CK slew rates are >=1.0V/ns
6.
These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester correlation.
7.
Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
8.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
9.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to
n-channel variation of the output drivers.
11. This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF
+/-310mV for a duration of up to 2ns.
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and
DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 =
0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tran-
sitions through the DC region must be monotonic.
15. tDAL = 2 clocks + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.
tCK is equal to the actual system clock cycle time.
Example: For DDR400(D4) at CL=3 and tCK = 5 ns,
tDAL = (15 ns / 5ns) + (18 ns / 5 ns) = (3.0) + (3.6)
Round up each non-integer to the next highest integer: = (3) + (4), tDAL = 7 clocks
16.
For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS - BL/2 x
tCK.
Input Setup / Hold Slew-rate
Delta tDS
Delta tDH
V/ns
ps
ps
0.5
0
0
0.4
+75
+75
0.3
+150
+150
I/O Input Level
Delta tDS
Delta tDH
mV
ps
ps
+280
+50
+50
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
Delta tDH
ns/V
ps
ps
0
0
0
+/-0.25
+50
+50
+/- 0.5
+100
+100
相關PDF資料 |
PDF描述 |
|---|---|
| HY5DU12422AT-X | 512Mb DDR SDRAM |
| HY5DU12822A | 512Mb DDR SDRAM |
| HY5DU12822ALT-X | 512Mb DDR SDRAM |
| HY5DU12822AT-X | 512Mb DDR SDRAM |
| HY5DU121622CTP | 512Mb(32Mx16) GDDR SDRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU12422AT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12422AT-H | 制造商:SK Hynix Inc 功能描述:128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| HY5DU12422AT-X | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12422B | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12422BLT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
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