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參數(shù)資料
| 型號： | HY57W2A1620HCST-B |
| 英文描述： | x16 SDRAM |
| 中文描述： | x16內(nèi)存 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 221K |
| 代理商： | HY57W2A1620HCST-B |
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T
HY5W26CF / HY57W281620HCT
Rev. 1.2 / Nov. 01
10
COMMAND TRUTH TABLE
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.
2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set.
Function
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
ADDR
A10/
AP
BA
Note
Mode Register Set
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
L
H
L
L
L
L
L
L
L
L
X
X
L
L
H
L
H
L
H
L
H
L
X
L
X
L
L
H
X
L
H
H
H
H
L
L
H
L
L
H
X
H
L
L
L
L
H
H
H
L
L
H
X
H
X
H
H
L
L
L
L
L
X
X
X
X
Op Code
Op Code
X
X
Row Address
V
Column
L
Column
H
Column
L
Column
H
X
H
X
L
X
X
X
X
X
X
2
2
Extended Mode Register Set
H
No Operation
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Device Deselect
Bank Active
Read
V
V
V
V
X
V
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
X
X
X
X
X
X
X
V
X
X
X
Precharge selected Bank
Burst stop
Data Write/Output Enable
Data Mask/Output Disable
Auto Refresh
L
L
X
H
X
H
X
H
X
V
L
L
X
H
X
H
X
H
X
V
H
H
X
H
X
H
X
H
X
V
Self Refresh Entry
Self Refresh Exit
1
Precharge Power Down
Entry
H
L
X
X
Precharge Power Down Exit
L
H
X
X
Clock Suspend Entry
H
L
X
X
Clock Suspend Exit
L
H
L
H
L
H
X
X
X
X
X
X
Deep Power Down Entry
H
H
L
Deep Power Down Exit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57W2A1620HCST-H | SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC |
| HY57W2A1620HCST-P | x16 SDRAM |
| HY57W2A1620HCST-S | SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC |
| HY5W26CF-P | x16 SDRAM |
| HY5W26CF-S | SDRAM|4X2MX16|CMOS|BGA|54PIN|PLASTIC |
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