參數(shù)資料
型號: HY57W2A1620HCLT-B
英文描述: x16 SDRAM
中文描述: x16內(nèi)存
文件頁數(shù): 13/24頁
文件大?。?/td> 221K
代理商: HY57W2A1620HCLT-B
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T
HY5W26CF / HY57W281620HCT
Rev. 1.2 / Nov. 01
14
Note :
1. H: Logic High, L: Logic Low, X: Don’t care, BA: Bank Address, AP: Auto Precharge.
2. All entries assume that CKE was active during the preceding clock cycle.
3. If both banks are idle and CKE is inactive, then in power down cycle
4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending
on the state of that bank.
5. If both banks are idle and CKE is inactive, then Self Refresh mode.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. Must satisfy burst interrupt condition.
9. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
10. Must mask preceding data which don’t satisfy tDPL.
11. Illegal if tRRD is not satisfied
12. Illegal for single bank, but legal for other banks in multi-bank devices.
13. Illegal for all banks.
14. Mode Register Set and Extended Mode Register Set is same command truth table except BA1.
相關(guān)PDF資料
PDF描述
HY57W2A1620HCLT-H SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC
HY57W2A1620HCLT-P x16 SDRAM
HY57W2A1620HCLT-S SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC
HY57W2A1620HCST-B x16 SDRAM
HY57W2A1620HCST-H SDRAM|4X2MX16|CMOS|TSOP|54PIN|PLASTIC
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