HT95C200/20P/300/30P
Rev. 0.10
8
October 1, 2002
Preliminary
Functional Description
Execution flow
The system clock for the telephone controller is derived
froma32768Hzcrystaloscillator.Abuilt-infrequencyup
conversion circuit provides dual system clock, namely;
32768Hz and 3.58MHz. The system clock is internally
divided into four non-overlapping clocks. One instruc-
tion cycle consists of four system clock cycles. Instruc-
tion fetching and execution are pipelined in such a way
that a fetch takes an instruction cycle while decoding
and execution takes the next instruction cycle. The
pipelining scheme causes each instruction to be effec-
tively executed in a instruction cycle. If an instruction
changes the program counter, two instruction cycles are
required to complete the instruction.
Program counter
PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of pro-
gram memory. After accessing a program memory word
to fetch an instruction code, the contents of the program
counter are incremented by 1. The program counter
then points to the memory word containing the next in-
struction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the program counter manipulates the pro-
gram transfer by loading the address corresponding to
each instruction. The conditional skip is activated by in-
structions. Once the condition is met, the next instruc-
tion, fetched during the current instruction execution, is
discarded and a dummy cycle replaces it to get the
proper instruction. Otherwise proceed to the next in-
struction.
The program counter lower order byte register
(PCL:06H) is a readable and write-able register. Moving
data into the PCL performs a short jump. The destina-
0
&
*
0
&
*
0
&
*
<
"
" ,
/
; @
"
" ,
A /
<
"
" ,
B
/
; @
"
" ,
/
<
"
" ,
B 0 /
; @
"
" ,
B
/
B
B 0
"
8
9
Execution flow
Mode
Program Counter
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
0
0
0
0
0
0
0
0
0
0
0
0
0
External interrupt
0
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 overflow
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 overflow
0
0
0
0
0
0
0
0
0
1
1
0
0
Peripheral interrupt
0
0
0
0
0
0
0
0
1
0
0
0
0
RTC interrupt
0
0
0
0
0
0
0
0
1
0
1
0
0
Dialer I/O interrupt
0
0
0
0
0
0
0
0
1
1
0
0
0
Skip
Program Counter+2
Loading PCL
*12
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, call branch
#12
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Note: *12~*0: Program counter bits
S12~S0: Stack register bits
#12~#0: Instruction code bits
@7~@0: PCL bits