參數(shù)資料
型號(hào)： HT95C30P
廠商： Holtek Semiconductor Inc.
英文描述： 8-Bit CID Type Phone Controller MCU
中文描述： 8位偵緝型電話MCU控制器
文件頁(yè)數(shù)： 13/50頁(yè)
文件大?。?/td> 324K
代理商： HT95C30P
HT95C200/20P/300/30P
Rev. 0.10
13
October 1, 2002
Preliminary
Interrupt
The telephone controller provides an external interrupt,
internal timer/event counter interrupt, a peripheral inter-
rupt, an internal real time clock interrupt and internal di-
aler I/O interrupt. The Interrupt Control Registers 0 and
Interrupt Control Register 1 both contains the interrupt
control bits that set the enable/disable and the interrupt
request flags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by hardware clearing the EMI
bit). This scheme may prevent any further interrupt nest-
ing. Other interrupt requests may occur during this inter-
val but only the interrupt request flag is recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 (INTC1) may be set to allow interrupt nesting.
If the stack is full, any other interrupt request will not be
acknowledged, even if the related interrupt is enabled,
until the stack pointer is decremented. If immediate ser-
vice is desired, the stack must be prevented from be-
coming full.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the pro-
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.
External interrupt is triggered by a high to low transition
of the INT/TMR1 pin and the interrupt request flag EIF
will be set. When the external interrupt is enabled, the
stackisnotfullandtheexternalinterruptisactive,asub-
routine call to location 04H will occur. The interrupt re-
quest flag EIF and EMI bits will be cleared to disable
other interrupts.
The Timer/Event Counter 0 interrupt is generated by a
timeout overflow and the interrupt request flag T0F will
be set. When the Timer/Event Counter 0 interrupt is en-
abled, the stack is not full and the T0F bit is set, a sub-
routine call to location 08H will occur. The interrupt
request flag T0F and EMI bits will be cleared to disable
further interrupts.
The Timer/Event Counter 1 interrupt is generated by a
timeout overflow and the interrupt request flag T1F will
be set. When the Timer/Event Counter 1 interrupt is en-
abled, the stack is not full and the T1F bit is set, a sub-
routine call to location 0CH will occur. The interrupt
request flag T1F and EMI bits will be cleared to disable
further interrupts.
The peripheral interrupt is activated when the
burst-cycle is finished or the FSK decoder detect the
ring signal or line reversal or FSK carrier signal or FSK
packet data. When these interrupts occurred, the inter-
rupt request flag PERF will be set. When the peripheral
interrupt is enabled, the stack is not full and the PERF is
set, a subroutine call to location 10H will occur. The in-
terrupt request flag PERF and EMI bits will be cleared to
disable other interrupts.
The real time clock interrupt is generated by a 1Hz RTC
generator. When the RTC time-out occurs, the interrupt
request flag RTCF will be set. When the RTC interrupt is
enabled, the stack is not full and the RTCF is set, a sub-
routine call to location 14H will occur. The interrupt re-
quest flag RTCF and EMI bits will be cleared to disable
other interrupts.
Register
Label
Bits
R/W
Function
INTC0
(0BH)
EMI
0
RW
Controls the master (global) interrupt (1=enabled; 0=disabled)
EEI
1
RW
Controls the external interrupt (1=enabled; 0=disabled)
ET0I
2
RW
Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
ET1I
3
RW
Controls the Timer/Event Counter1 interrupt (1=enabled; 0=disabled)
EIF
4
RW
External interrupt request flag (1=active; 0=inactive)
T0F
5
RW
Timer/Event Counter 0 request flag (1=active; 0=inactive)
T1F
6
RW
Timer/Event Counter1 request flag (1=active; 0=inactive)
7
RO
Unused bit, read as 0
INTC1
(1EH)
EPERI
0
RW
Control the peripheral interrupt (1=enable; 0=disable)
ERTCI
1
RW
Control the real time clock interrupt (1=enable; 0=disable)
EDRI
2
RW
Control the dialer I/O interrupt (1=enable; 0=disable)
3
RO
Unused bit, read as 0
PERF
4
RW
Peripheral interrupt request flag (1=active; 0=inactive)
RTCF
5
RW
Internal real time clock interrupt request flag (1=active; 0=inactive)
DRF
6
RW
Internal dialer I/O interrupt request flag (1=active: 0=inactive)
7
RO
Unused bit, read as 0
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