HT95C200/20P/300/30P
Rev. 0.10
17
October 1, 2002
Preliminary
By examining the processor status flags PD and TO, the
software program can distinguish between the different
chip resets .
TO
PD
Reset Condition
0
0
Power on reset
u
u
External reset during Normal mode or
Green mode
0
1
External reset during Sleep mode or
Idle mode
1
u
WDT time-out during Normal mode or
Green mode
1
1
WDT time-out during Sleep mode or
Idle mode
Note: u means unchanged
The functional units chip reset status are shown below:
Program Counter
000H
Interrupt
Disabled
Prescaler
Cleared
WDT
Cleared
After a master reset, WDT
begins counting.
(If WDT function is enabled
by mask option)
Timer/EventCounter0/1 Off
Input/output Port
Input mode
Stack Pointer
Pointstothetopofthestack
7
"
7
8 "
5
D
1
' A C
"
8
7
"
A
; @
8 " " "
;
"
Reset configuration
;
>
"
A
" "
Reset timing chart
When the reset conditions occurred, some registers may be changed or unchanged.
Register
Addr.
Reset Conditions
Power On
RES Pin
RES Pin
(Sleep/Idle)
WDT
WDT
(Sleep/Idle)
IAR0
00H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP0
01H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
IAR1
02H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
03H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
04H
---0 0000
---0 0000
---0 0000
---0 0000
---u uuuu
ACC
05H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
06H
0000H
0000H
0000H
0000H
0000H
TBLP
07H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
08H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
09H
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
0AH
--00 xxxx
--uu uuuu
--01 uuuu
--1u uuuu
--11 uuuu
INTC0
0BH
-000 0000
-000 0000
-000 0000
-000 0000
uuuu uuuu
TMR0H
0CH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0L
0DH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
0EH
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
TMR1H
0FH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
10H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu