HT82M9BEE/HT82M9BAE
Rev. 1.20
10
August 13, 2007
a branch to a subroutine at a specified location in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register or status
register (STATUS) are altered by the interrupt service
program which corrupts the desired control sequence,
the contents should be saved in advance.
The USB interrupts are triggered by the following USB
events and the related interrupt request flag (USBF; bit
4 of the INTC) will be set.
Access of the corresponding USB FIFO from PC
The USB suspend signal from PC
The USB resume signal from PC
USB Reset signal
When the interrupt is enabled, the stack is not full and
the external interrupt is active, a subroutine call to loca-
tion 04H will occur. The interrupt request flag (USBF)
and EMI bits will be cleared to disable other interrupts.
When the PC Host access the FIFO of the
HT82M9BEE/HT82M9BAE, the corresponding request
bit of the USR is set, and a USB interrupt is triggered. So
user can easily decide which FIFO is accessed. When
the interrupt has been served, the corresponding bit
should be cleared by firmware. When the
HT82M9BEE/HT82M9BAE receives a USB Suspend
signal from the Host PC, the suspend line (bit0 of the
USC) of the HT82M9BEE/HT82M9BAE is set and a
USB interrupt is also triggered.
When the HT82M9BEE/HT82M9BAE receives a Re-
sume signal from the Host PC, the resume line (bit3 of
the USC) of the HT82M9BEE/HT82M9BAE are set and
a USB interrupt is triggered.
Whenever a USB reset signal is detected, the USB in-
terrupt is triggered and URST_Flag bit of the USC regis-
ter is set. When the interrupt has been served, the bit
should be cleared by firmware.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (bit 5 of the INTC), caused by a Timer 0
overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further in-
terrupts.
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enable; 0=disable)
1
EUI
Controls the USB interrupt (1=enable; 0= disable)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)
4
USBF
USB interrupt request flag (1=active; 0=inactive)
5
T0F
Internal Timer/Event Counter 0 request flag (1:active; 0:inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1:active; 0:inactive)
7
Unused bit, read as 0
INTC (0BH) Register
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
takeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by
executing the HALT instruction.
5
TO
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is
set by a WDT time-out.
6~7
Unused bit, read as 0
Status (0AH) Register