參數(shù)資料
型號(hào)： HT82J97E
廠商： Holtek Semiconductor Inc.
英文描述： USB Joystick Encoder 8-Bit OTP MCU
中文描述： USB搖桿編碼器8位微控制器檢察官辦公室
文件頁數(shù)： 9/46頁
文件大小： 314K
代理商： HT82J97E
HT82J97E
Rev. 1.30
9
May 10, 2004
The USB interrupts are triggered by the following USB
events and the related interrupt request flag (USBF; bit
4 of the INTC) will be set.
Access of the corresponding USB FIFO from PC
suspend signal from PC
resume signal from PC
USB Reset signal
When the interrupt is enabled, the stack is not full and
the external interrupt is active, a subroutine call to loca-
tion 04H will occur. The interrupt request flag (USBF)
and EMI bits will be cleared to disable other interrupts.
When the PC Host access the FIFO of the HT82J97E,
the corresponding request bit of the USR is set, and a
USB interrupt is triggered. So user can easily decide
which FIFO is accessed. When the interrupt has been
served, the corresponding bit should be cleared by firm-
ware. When the HT82J97E receives a USB Suspend
signal from the Host PC, the suspend line (bit0 of the
USC) of the HT82J97E is set and a USB interrupt is also
triggered.
WhentheHT82J97EreceivesaResumesignalfromthe
Host PC, the resume line (bit3 of the USC) of the
HT82J97E is set and a USB interrupt is triggered.
Whenever a USB reset signal is detected, the USB in-
terrupt is triggered and URST_Flag bit of the USC regis-
ter is set. When the interrupt has been served, the bit
should be cleared by firmware.
The internal timer/even counter interrupt is initialized by
settingthetimer/eventcounterinterruptrequestflag(;bit
6 of the INTC), caused by a timer overflow. When the in-
terruptisenabled,thestackisnotfullandtheTFisset,a
subroutine call to location 0CH will occur. The related in-
terrupt request flag (TF) will be reset and the EMI bit
cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, RET or RETI
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
No.
Interrupt Source
Priority Vector
a
USB interrupt
1
04H
b
Timer/Event Counter overflow
2
0CH
The timer/event counter interrupt request flag (TF), USB
interrupt request flag (USBF), enable timer/event coun-
ter interrupt bit (ETI), enable USB interrupt bit (EUI) and
enable master interrupt bit (EMI) constitute an interrupt
control register (INTC) which is located at 0BH in the
data memory. EMI, EUI and ETI are used to control the
enabling/disabling of interrupts. These bits prevent the
requested interrupt from being serviced. Once the inter-
rupt request flags (TF, USBF) are set, they will remain in
the INTC register until the interrupts are serviced or
cleared by a software instruction.
It is recommended that a program does not use the
CALL subroutine within the interrupt subroutine. Inter-
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and enabling the interrupt is not well
controlled, the original control sequence will be dam-
aged once the CALL operates in the interrupt subrou-
tine.
Oscillator Configuration
There is an oscillator circuit in the microcontroller.
This oscillator is designed for system clocks. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
A crystal across OSC1 and OSC2 is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. In stead of
a crystal, a resonator can also be connected between
OSC1 and OSC2 to get a frequency reference, but two
external capacitors in OSC1 and OSC2 are required.
The HT82J97E can operate in 6MHz or 12MHz system
clocks. In order to make sure that the USBSIE functions
properly, user should correctly configure the SCLKSEL
bit of the SCC Register. The default system clock is
12MHz.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDToscillator still works within
a period of approximately 31 s. The WDT oscillator can
be disabled by ROM code option to conserve power.
Watchdog Timer
WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), or instruction clock (sys-
tem clock divided by 4), determine by ROM code option.
This timer is designed to prevent a software malfunction
or sequence from jumping to an unknown location with
unpredictable results. The Watchdog Timer can be dis-
abled by ROM code option. If the Watchdog Timer is dis-
!
, (
!
, ,
System Oscillator
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