參數(shù)資料
型號: HT82J97E
廠商: Holtek Semiconductor Inc.
英文描述: USB Joystick Encoder 8-Bit OTP MCU
中文描述: USB搖桿編碼器8位微控制器檢察官辦公室
文件頁數(shù): 13/46頁
文件大?。?/td> 314K
代理商: HT82J97E
HT82J97E
Rev. 1.30
13
May 10, 2004
Label (TMRC)
Bits
Function
0~2
Unused bit, read as 0
TE
3
Defines the TMR active edge of the timer/event counter
(0=active on low to high; 1=active on high to low)
TON
4
Enable/disable the timer counting
(0=disable; 1=enable)
5
Unused bit, read as 0
TM0
TM1
6
7
Defines the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC Register
Timer/Event Counter
A timer/event counter (TMR) is implemented in the
microcontroller.
The timer/event counter contains a 16-bit programma-
ble count-up counter and the clock may come from an
external source or from the system clock divided by 4.
Using the internal clock source, there is only 1 reference
time-base for the timer/event counter. The internal clock
source is coming from f
SYS
/4. The external clock input
allows the user to count external events, measure time
intervals or pulse widths.
There are 3 registers related to the timer/event counter;
TMRH (0FH), TMRL (10H), TMRC (11H). Writing TMRL
will only put the written data to an internal lower-order
byte buffer (8 bits) and writing TMRH will transfer the
specified data and the contents of the lower-order byte
buffer to TMRH and TMRL preload registers, respec-
tively. The timer/event counter preload register is
changed by each writing TMRH operations. Reading
TMRH will latch the contents of TMRH and TMRL coun-
ters to the destination and the lower-order byte buffer,
respectively. Reading the TMRLwill read the contents of
the lower-order byte buffer. The TMRC is the
timer/event counter control register, which defines the
operating mode, counting enable or disable and active
edge.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
whichmeansthattheclocksourcecomesfromanexter-
nal (TMR) pin. The timer mode functions as a normal
timer with the clock source coming from the f
SYS
/4
(Timer). The pulse width measurement mode can be
used to count the high or low level duration of the exter-
nal signal (TMR). The counting is based on the f
SYS
/4.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFFFH. Once
overflow occurs, the counter is reloaded from the
timer/event counter preload register and generates the
interrupt request flag (TF; bit 6 of the INTC) at the same
time.
In the pulse width measurement mode with the TON and
TE bits equal to one, once the TMR has received a tran-
sient from low to high (or high to low if the TE bit is 0 ) it
will start counting until the TMR returns to the original
level and resets the TON. The measured result will re-
main in the timer/event counter even if the activated
transient occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it re-
ceives further transient pulse. Note that, in this operat-
ing mode, the timer/event counter starts counting not
according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter preload register
and issues the interrupt request just like the other two
modes. To enable the counting operation, the timer ON
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Timer/Event Counter
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