HT82J97E
Rev. 1.30
20
May 10, 2004
The device with remote wake-up function can wake-up
the USB Host by sending a wake-up pulse through
RMWK (bit 1 of USC). Once the USB Host receive the
wake-up signal from the HT82J97E, it will send a Re-
sume signal to the device. The timing is as follows:
To Configure the HT82J97E as PS2 Device
The HT82J97E can be defined as a USB interface or a
PS2 interface by configuring the SPS2 (bit 4 of the USR)
and SUSB (bit 5 of the USR). If SPS2=1, and SUSB=0,
the HT82J97E is defined as PS2 interface, pin USBD- is
now defined as PS2 Data pin and USBD+ is now de-
fined as PS2 Clk pin. The user can easily read or write to
the PS2 Data or PS2 Clk pin by accessing the corre-
sponding bit PS2DAI (bit 4 of the USC), PS2CKI (bit 5 of
the USC), PS2DAO (bit 6 of the USC) and S2CKO (bit 7
of the USC) respectively.
The user should make sure that in order to read the data
properly, the corresponding output bit must be set to 1 .
For example, if user wants to read the PS2 Data by
reading PS2DAI, the PS2DAO should be set to 1 . Oth-
erwise it always read a 0 .
If SPS2=0, and SUSB=1, the HT82J97E is defined as a
USB interface. Both the USBD- and USBD+ are driven
by the USB SIE of the HT82J97E. User only writes or
reads the USB data through the corresponding FIFO.
Both SPS2 and SUSB default is 0 .
To Configure the ADC Block
The HT82J97E has built-in an 8-bit A/D converter with 6
channels (PB0~PB5). In order to make the A/D con-
verter more flexible, there are two modes: External Ref-
erence voltage and Internal Reference voltage. It can be
easily configured by setting the ADREF (bit 6 of the
USR). For External Reference voltage, the reference
voltage of the A/D converter comes from an external
PB6/VRL and PB7/VRH pins. Otherwise, the reference
voltage is coming from the VDD and VSS of the MCU.
PB0~PB5 is the 6-channel input of the A/D converter, it
is easy to define which channel is converting by config-
uring ACS2~ACS0 (bit 2~0 of the ADSC). Also there are
four converter clock sources to be selected by setting
ADCS1(bit4oftheADSC),ADCS0(bit3oftheADSC).
Once the ADON (bit 6 of the ADSC) is set, it sends the
start pulse through START (bit 5 of ADSC). The A/D
converter will be in operation. There are EOCB (bit 7 of
the ADSC) to indicate whether the A/D converter is busy
or not. The EOCB is cleared when the conversion is
completed. User can read the converter data by reading
the register ADR. In order to meet 500 A suspend cur-
rent spec., user should disable the A/D by clearing
ADON before jumping to suspend mode.
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The following is an A/D converter timing diagram:
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