參數(shù)資料
型號(hào)： HT82J30A
廠商： Holtek Semiconductor Inc.
英文描述： 16 Channel A/D MCU with SPI Interface
中文描述： 16通道A / D轉(zhuǎn)換，SPI接口單片機(jī)
文件頁數(shù)： 16/47頁
文件大?。?/td> 312K
代理商： HT82J30A
HT82J30R/HT82J30A
Rev. 1.00
16
December 20, 2006
write 1 . The input source also depends on the control
register. If the control register bit is 1 , the input will
read the pad state. If the control register bit is 0 , the
contents of the latches will move to the internal bus. The
latter is possible in the read-modify-write instruction.
For output function, all I/Os except PB2, PB3, PD2, PD7
are CMOS types. There are options to define PB2, PB3,
PD2, PD7 as either CMOS or NMOS types. These con-
trol registers are mapped to locations 13H, 15H,
17H,19H and 23H.
After a device reset, these input/output lines remain at
high levels or a floating state, depending upon the
pull-high configuration options. Each bit of these in-
put/output latches can be set or cleared using the SET
[m].i and CLR [m].i instructions.
Some instructions first input data and then follow the
output operations. For example,
SET [m].i ,
CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device.
Each I/O line has a pull-high option. Once a pull-high op-
tion is selected, the I/O line has a pull-high resistor
connected, otherwise, there are none. Take note that a
non-pull-high I/O line operating as an input will be in a
floating state.
Pin PA3 is pin-shared with the PFD signal. If the PFD
configuration option is selected, the output signal on
PA3, if setup as an output, will be the PFD signal gener-
ated by the timer/event counter overflow signal. If setup
as an input then the pin will retain its input function.
Once the PFD configuration option is selected, the PFD
output signal is controlled by the PA3 data register. Writ-
ing a 1 to the PA3 data register will enable the PFD
output function and writing 0 will force pin PA3 to re-
mainat 0 .TheI/OfunctionsofPA3are shownbelow.
I/O
Mode
I/P
(Normal)
O/P
(Normal)
I/P
(PFD)
O/P
(PFD)
PA3
Logical
Input
Logical
Output
Logical
Input
PFD
(Timer on)
Note:
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
PA6, PA5 and PA4 are pin-shared with the INT0, INT1
and TMR pins respectively.
PB and PC can also be used as A/D converter inputs.
The A/D function will be described later. There are two
SPI interfaces which are shared with pins PD1~PD4,
PD7 and PF0~PF2. The SPI function will be described
later. There is a PWM function shared with pin PD0. If
the PWM function is enabled, the PWM signal will ap-
pear on pin PD0 (if PD0 is setup as an output). Writing a
1 to the PD0 data register will enable the PWM output
function and writing a 0 will force the PD0 to remain at
0 . The I/O functions of PD0 are shown in the table.
I/O
Mode
I/P
(Normal)
O/P
(Normal)
I/P
(PWM)
O/P
(PWM)
PD0
Logical
Input
Logical
Output
Logical
Input
PWM
It is recommended that unused or not bonded out I/O
.
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Input/Output Ports
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