HT82J30R/HT82J30A
Rev. 1.00
15
December 20, 2006
The bit0~bit2 of the TMRC can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter. The overflow signal of the
timer/event counter can be used to generate the PFD
signal.
Input/Output Ports
There are 35 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC, PD and PF,
which are mapped to the data memory of [12H], [14H],
[16H],[18H]and[22H]respectively.AlloftheseI/Oports
can be used for input and output operations. For input
operation, these ports are non-latching, that is, the in-
puts must be ready at the T2 rising edge of instruction
MOV A,[m] (m=12H, 14H, 16H, 18H or 22H). For output
operation, all the data is latched and remains unchanged
until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC, PFC) to control the input/output configura-
tion. With this control register, a CMOS output or
Schmitt trigger input with or without pull-high resistor
structures can be reconfigured dynamically (i.e.
on-the-fly) under software control. To function as an in-
put, the corresponding latch of the control register must
Bit No.
Label
Function
0
1
2
PSC0
PSC1
PSC2
Defines the prescaler stages, PSC2, PSC1, PSC0=
000: f
INT
=f
SYS
001: f
INT
=f
SYS
/2
010: f
INT
=f
SYS
/4
011: f
INT
=f
SYS
/8
100: f
INT
=f
SYS
/16
101: f
INT
=f
SYS
/32
110: f
INT
=f
SYS
/64
111: f
INT
=f
SYS
/128
3
TE
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
TON
Enable or disable the timer counting
(0=disable; 1=enable)
5
Unused bits, read as 0
6
7
TM0
TM1
Defines the operating mode (TM1, TM0)=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC (0EH) Register
2 & 4
&
" ' )
'
2
5 7 1 "
"
8
2
'
" &
5 7 1 "
"
8
1
&
2
'
8 * 2 G
!
.
5 7 &
& #
2
5 7
*
3
*
-
; >
<
!
4
" #
"
Timer/Event Counter