HT82J30R/HT82J30A
Rev. 1.00
11
December 20, 2006
prevent the requested interrupt from being serviced.
Once the interrupt request flags (TF, EIF, ADF) are set,
they will remain in the INTC register until the interrupts
are serviced or cleared by a software instruction.
ItisrecommendedthataprogramdoesnotusetheCALL
subroutine within the interrupt subroutine. Interrupts of-
ten occur in an unpredictable manner or need to be ser-
viced immediately in some applications. If only one stack
is left and enabling the interrupt is not well controlled, the
original control sequence will be damaged if a CALL in-
struction is executed in the interrupt subroutine.
Oscillator configuration
There are 2 oscillator circuits in the microcontroller.
Both of them are designed for system clocks, namely
the external RC oscillator, the external Crystal oscillator
and the internal RC oscillator, the choice of which is de-
termined by configuration options. The Power Down
mode stops the system oscillator to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VDD is required and the resistance must
range from 47k
by 4, is available on OSC2, which can be used to syn-
chronize external logic. The RC oscillator provides the
most cost effective solution. However, the oscillation
frequency may vary with VDD, temperature and pro-
cess variations. It is, therefore, not suitable for timing
sensitive operations where an accurate oscillator fre-
quency is desired.
to 750k . The system clock, divided
If the Crystal oscillator is used, a crystal across OSC1 and
OSC2 is needed to provide the feedback and phase shift
required for the oscillator. No other external components
are required. Instead of a crystal, a resonator can also be
connected between OSC1 and OSC2 to obtain a fre-
quency reference, but two external capacitors connected
between OSC1 and OSC2 and ground are required.
The WDT oscillator is a free running on-chip RC oscillator,
and no external components are required. Even if the sys-
tem enters the power down mode, the system clock is
stopped, but the WDT oscillator still works within a period
of 65 s at 5V. The WDT oscillator can be disabled by op-
tions to conserve power.
Watchdog Timer
WDT
The clock source of WDTis implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4), chosen via a configuration op-
tion. This timer is designed to prevent software
malfunctions or the program jumping to unknown loca-
tions. The Watchdog Timer can be disabled by a config-
uration option. If the Watchdog Timer is disabled, all the
executions related to the WDT result in no operation.
If the internal oscillator, which is an RC oscillator with a
nominal period of 65 s at 5V, is selected, it is first di-
vided by 32768~65536 to get a time-out period of ap-
proximately 2.1s~4.3s. This time-out period may vary
with temperature, VDD and process variations. If the
WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the HALTstate the WDTmay stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT instruction will stop the system
clock.
The WDT overflow under normal operation will initialize
a chip reset and set the status bit TO . But in the
Power-down mode, the overflow will initialize a warm
reset , and only the program counter and the SP are re-
set to zero. To clear the contents of the WDT, three
methods are adopted; an external reset (a low level on
the RES pin), a software instruction or a HALT instruc-
tion. The software instructions include CLR WDT and
theotherset
two types of instruction, only one can be active depend-
CLRWDT1 and CLRWDT2 .Ofthese
ingontheconfigurationoption
CLRWDTtimesselec-
tion option . If the CLR WDT is selected (i.e. CLR
WDT times equal one), any execution of the
CLR
WDT instruction will clear the WDT. In the case that
CLR WDT1 and CLR WDT2 are chosen (i.e. CLR
WDT times equal two), these two instructions must be
executed to clear the WDT; otherwise, the WDT may re-
set the chip as a result of a time-out.
% &
2 # /
5 7 A "
! "
2 #
4
*
0 7 A "
4
"
7
*
- *
(
4
Watchdog Timer
% &
2
& # " 2 2
& # " 2 2
!
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"
*
3
/
System Oscillator