參數(shù)資料
型號(hào): HT49R50A
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit High Performance High speed Microcontroller(8位、高性能、高速微控制器)
中文描述: 8位高性能高速微控制器(8位,高性能,高速微控制器)
文件頁數(shù): 48/51頁
文件大?。?/td> 320K
代理商: HT49R50A
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (one of
the data memories) are interchanged.
Operation
[m].3~[m].0
[m].7~[m].4
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
SWAPA [m]
Swap data memory-place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are inter-
changed, writing the result to the accumulator. The contents of the data
memory remain unchanged.
Operation
ACC.3~ACC.0
ACC.7~ACC.4
[m].7~[m].4
[m].3~[m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
SZA [m]
Move data memory to , skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If
the contents is 0, the following instruction, fetched during the current in-
struction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1
cycle).
Operation
Skip if [m]=0, ACC
[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
HT49R50A
48
November 29, 2000
相關(guān)PDF資料
PDF描述
HT49R50 8-BIT MICROCONTROLLER
HT5D048 0.8m CMOS High Speed Gate Array(0.8m CMOS高速門陣列)
HT5D028 0.8m CMOS High Speed Gate Array(0.8m CMOS高速門陣列)
HT5D064 0.8m CMOS High Speed Gate Array(0.8m CMOS高速門陣列)
HT5F240 0.8m CMOS High Speed Gate Array(0.8m CMOS高速門陣列)
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