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參數(shù)資料
| 型號： | HT49R50A |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit High Performance High speed Microcontroller(8位、高性能、高速微控制器) |
| 中文描述： | 8位高性能高速微控制器（8位，高性能，高速微控制器） |
| 文件頁數(shù)： | 25/51頁 |
| 文件大小： | 320K |
| 代理商： | HT49R50A |
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HT49R50A
25
November 29, 2000
If you choose NMOS (input), each bit on the port
(PA0~PA7)canbeconfiguredasawake-upinput.
PBcanonlybeusedforinputoperation,andeach
bit on the port can be configured with pull-high
resistor.PCcanbeconfiguredasCMOSoutputor
NMOSinput/outputwithorwithoutpull-highre-
sistor by options. All the port for the input opera-
tion (PA, PB and PC), these ports are
non-latched,thatis,theinputsshouldbereadyat
the T2 rising edge of the instruction MOV A,
[m] (m=12H or 14H). For PA, PC output opera-
tion, all data are latched and remain unchanged
until the output latch is rewritten.
When the PA and PC structures are open drain
NMOS type, it should be noted that, before
reading data from the pads, a 1
written to the related bits to disable the NMOS
device. That is executing first the instruction
"SET [m].i" (i=0~7 for PA) to disable related
NMOS device, and then "MOV A, [m]" to get
stable data.
should be
After chip reset, these input lines remain at the
high level or are left floating (by options). Each
bit of these output latches can be set or cleared
by the "MOV [m], A" (m=12H or 16H) instruc-
tion.
Some instructions first input data and then fol-
low the output operations. For example, "SET
[m].i", "CLR [m].i", "CPL [m]", "CPLA[m]" read
the entire port states into the CPU, execute the
defined operations (bit-operation), and then
write the results back to the latches or to the ac-
cumulator. When a PA or PC line is used as an
I/O line, the related PA or PC line options
should be configured as NMOS with or without
pull-high resistor. Once a PA or PC line is se-
lected as a CMOS output, the I/O function can-
not be used.
The input state of a PA or PC line is read from
the related PAor PC pad. When the PAor PC is
configured as NMOS with or without pull-high
resistor, one should be careful when applying a
read-modify-write instruction to PA or PC.
Since the read-modify-write will read the entire
port state (pads state) firstly, execute the speci-
fied instruction and then write the result to the
port data register. When the read operation is
executed, a fault pad state (caused by the load
effect or floating state) may be read. Errors will
then occur.
There are three function pins that share with
the PA port: PA0/BZ, PA1/BZ and PA3/PFD.
The BZ and BZ are buzzer driving output pair
and the PFD is a programmable frequency di-
vider output. If the user wants to use the BZ/BZ
or PFD function, the related PA port should be
set as a CMOS output. The buzzer output sig-
nals are controlled by PA0 and PA1 data regis-
ters and defined in the following table.
PA1 Data
Register
PA0 Data
Register
PA0/PA1 Pad State
0
0
PA0=BZ, PA1=BZ
1
0
PA0=BZ, PA1=0
X
1
PA0=0, PA1=0
Note: X stands for undefined
The PFD output signal function is controlled by
the PA3 data register and the timer/event coun-
ter state. The PFD output signal frequency is
also dependent on the timer/event counter
overflow period. The definitions of PFD control
signal and PFD output frequency are listed in
the following table.
Timer Timer Preload Value PA3 Data Register
PA3 Pad State
PFD Frequency
OFF
X
0
U
X
OFF
X
1
0
X
ON
N
0
PFD
f
INT
/[2 (256 N)]
X
ON
N
1
0
Note:
X stands for undefined
U stands for unknown
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