參數(shù)資料
型號: HT49R50A
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit High Performance High speed Microcontroller(8位、高性能、高速微控制器)
中文描述: 8位高性能高速微控制器(8位,高性能,高速微控制器)
文件頁數(shù): 38/51頁
文件大?。?/td> 320K
代理商: HT49R50A
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1 s comple-
ment). Bits which previously contained a 1 are changed to 0 and vice-versa.
The complemented result is stored in the accumulator and the contents of
the data memory remain unchanged.
Operation
ACC
[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Code Decimal) code.
The accumulator is divided into two nibbles. Each nibble is adjusted to the
BCD code and an internal carry (AC1) will be done if the low nibble of the ac-
cumulator is greater than 9. The BCD adjustment is done by adding 6 to the
originalvalueiftheoriginalvalueisgreaterthan9oracarry(ACorC)isset;
otherwise the original value remains unchanged. The result is stored in the
data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0
else [m].3~[m].0)
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4
else [m].7~[m].4
(ACC.3~ACC.0)+6, AC1=AC
(ACC.3~ACC.0), AC1=0
ACC.7~ACC.4+6+AC1,C=1
ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
DEC [m]
Decrement data memory
Description
Data in the specified data memory is by 1.
Operation
[m]
[m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
HT49R50A
38
November 29, 2000
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