HT49R50A
30
November 29, 2000
No.
Options
7
Wake-up selection. This option defines the wake-up capability. External I/O pins (PA
only) all have the capability to wake-up the chip from a HALT by a falling edge.
8
Pull-high selection. This option is to decide whether the pull-high resistance is visible or
not on the PA0~PA3 and PC. (PB and PA4~PA7 are always pull-high)
9
PA0~PA3 and PC0~PC3 CMOS or NMOS selection.
The structure of PA0~PA3 and PC0~PC3 each 4 bits can be selected as CMOS or NMOS
individually. When the CMOS is selected, the related pins only can be used for output op-
erations. When the NMOS is selected, the related pins can be used for input or output op-
erations. (PA4~PA7 are always NMOS)
10
Clock source selection of timer/event counter 0. There are two types of selection: system
clock or system clock/4.
11
Clock source selection of timer/event counter 1. There are three types of selection: TMR0
overflow, system clock or Time Base overflow.
12
I/O pins share with other functions selection.
PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs.
PA3/PFD: PA3 can be set as I/O pins or PFD output.
13
LCD common selection. There are three types of selection: 2 common (1/2 duty) or 3 com-
mon (1/3 duty) or 4 common (1/4 duty). If the 4 common is selected, the segment output
pin SEG32 will be set as a common output.
14
LCD bias power supply selection
There are two types of selection: 1/2 bias or 1/3 bias
15
LCD bias type selection
This option is to determine what kind of bias is selected, R type or C type.
16
LCD driver clock selection. There are seven types of frequency signals for the LCD driver
circuits: f
S
/2
2
~f
S
/2
8
. "F
S
" means the clock source selection by options.
17
LCD ON/OFF at HALT selection
18
LVD voltage selection
There are two type of selection: 2.2V or 3.3V (2.2V for power on protection)
19
LVR selection
LVR has enable or disable options
20
LVD selection
LVD has enable or disable options
21
PFD selection
If PA3 is set as PFD output, there are two types of selection; One is PFD0 as the PFD out-
put, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of
the timer/event counter 0, timer/event counter 1 respectively.