參數(shù)資料
型號(hào)： HT48RA3
廠商： Holtek Semiconductor Inc.
英文描述： 8-Bit Remote Type OTP MCU
中文描述： 8位單片機(jī)的遠(yuǎn)程型檢察官辦公室
文件頁(yè)數(shù)： 8/36頁(yè)
文件大?。?/td> 245K
代理商： HT48RA3
HT48RA3
Rev. 1.20
8
May 12, 2003
The internal Timer/Even Counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
flag (T1F;bit 6 of INTC), caused by a timer 1 overflow.
When the interrupt is enabled, the stack is not full and
the T1F is set, a subroutine call to location 0CH will oc-
cur. The related interrupt request flag (T1F) will be reset
and the EMI bit cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, RET or RETI
may be invoked. RETI will set the EMI bit to enable an in-
terrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
No.
Interrupt Source
Priority Vector
a
External Interrupt
1
04H
b
Timer/Event Counter 0 Overflow
2
08H
c
Timer/Event Counter 1 Overflow
3
0CH
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F), external interrupt request flag (EIF), enable
Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), en-
able external interrupt bit (EEI) and enable master inter-
rupt bit (EMI) constitute an interrupt control register
(INTC) which is located at 0BH in the data memory. EMI,
EEI, ET0I and ET1I are used to control the enabling/dis-
abling of interrupts. These bits prevent the requested in-
terrupt from being serviced. Once the interrupt request
flags(T0F,T1F,EIF)areset,theywillremainintheINTC
register until the interrupts are serviced or cleared by a
software instruction.
It is recommended that a program does not use the
CALL subroutine within the interrupt subroutine. In-
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-
aged once the CALL operates in the interrupt subrou-
tine.
Oscillator Configuration
There are 2 oscillator circuits in the MCU.
There are 2 oscillator circuits implemented in the mi-
cro-controller.
Both of them are designed for system clocks, namely
the RC oscillator and the crystal oscillator, which are de-
termined by options. No matter what oscillator type is
selected, the signal provides the system clock. The
HALT mode stops the system oscillator and resists the
external signal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance should
range from 100k
by 4, is available on OSC2, which can be used to syn-
chronize external logic. The internal RC oscillator pro-
vides the most cost effective solution. However, the
frequency of oscillation may vary with VDD, tempera-
tures and the chip itself due to process variations. It is,
therefore, not suitable for timing sensitive operations
where an accurate oscillator frequency is desired.
to 820k . The system clock, divided
If the crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
Register
Bit No.
Label
Function
INTC
(0BH)
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
1
EEI
Controls the external interrupt (1= enabled; 0= disabled)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1= enabled; 0= disabled)
4
EIF
External interrupt request flag (1= active; 0= inactive)
5
T0F
Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1= active; 0= inactive)
7
Unused bit, read as 0
INTC register
&
!
,
#
!
,
#
!
,
"
,
#
1
System oscillator
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