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參數(shù)資料
| 型號： | HT48E06 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit I/O Type MCU (With EEPROM) |
| 中文描述： | 8位I / O型微控制器（帶EEPROM） |
| 文件頁數(shù)： | 10/43頁 |
| 文件大小： | 346K |
| 代理商： | HT48E06 |
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HT48E06
Rev. 0.00
10
January 12, 2004
Preliminary
active, a subroutine call to location 04H will occur. The
interrupt request flag (EIF) and EMI bits will be cleared
to disable other interrupts.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF; bit 5 of the INTC), caused by a timer overflow.
When the interrupt is enabled, the stack is not full and
the TF bit is set, a subroutine call to location 08H will oc-
cur. The related interrupt request flag (TF) will be reset
and the EMI bit cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, RET or RETI
may be invoked. RETI will set the EMI bit to enable an in-
terrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
No.
Interrupt Source
Priority Vector
a
External Interrupt
1
04H
b
Timer/Event Counter Overflow
2
08H
The timer/event counter interrupt request flag (TF), ex-
ternal interrupt request flag (EIF), enable timer/event
counter interrupt bit (ETI), enable external interrupt bit
(EEI) and enable master interrupt bit (EMI) constitute an
interrupt control register (INTC) which is located at 0BH
in the data memory. EMI, EEI, ETI are used to control
the enabling/disabling of interrupts. These bits prevent
the requested interrupt from being serviced. Once the
interrupt request flags (TF, EIF) are set, they will remain
in the INTC register until the interrupts are serviced or
cleared by a software instruction.
It is recommended that a program does not use the
CALL subroutine within the interrupt subroutine. In-
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-
aged once the CALL operates in the interrupt subrou-
tine.
Oscillator Configuration
There are 2 oscillator circuits in the microcontroller.
All of them are designed for system clocks, namely, ex-
ternal RC oscillator and external Crystal oscillator,
which are determined by options. No matter what oscil-
lator type is selected, the signal provides the system
clock. The HALT mode stops the system oscillator and
ignores an external signal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VDD is required and the resistance must
range from 24k
4, is available on OSC2, which can be used to synchro-
nize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency of oscil-
lation may vary with VDD, temperatures and the chip it-
self due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accu-
rate oscillator frequency is desired.
to 1M . The system clock, divided by
If a Crystal oscillator is used, a crystal across OSC1 and
OSC2 is needed to provide the feedback and phase
shift required for the oscillator. No other external compo-
nents are required. In stead of a crystal, a resonator can
also be connected between OSC1 and OSC2 to obtain
a frequency reference, but two external capacitors in
OSC1 and OSC2 are required.
The WDToscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode and the sys-
Register
Bit No.
Label
Function
INTC
(0BH)
0
EMI
Controls the master (global) interrupt (1= enable; 0= disable)
1
EEI
Controls the external interrupt (1= enable; 0= disable)
2
ETI
Controls the Timer/Event Counter 0 interrupt (1= enable; 0= disable)
3
Unused bit, read as 0
4
EIF
External interrupt request flag (1= active; 0= inactive)
5
TF
Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)
6
Unused bit, read as 0
7
Unused bit, read as 0
INTC Register
,
( !
* ! ! ( #
* ! ! ( #
)
'
* '
) 9
System Oscillator
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