參數(shù)資料
型號(hào)： HT46R63
廠商： Holtek Semiconductor Inc.
英文描述： A/D with LCD Type 8-Bit MCU
中文描述： 在A / D液晶型8位微控制器
文件頁(yè)數(shù)： 21/44頁(yè)
文件大?。?/td> 328K
代理商： HT46R63
HT46R63/HT46C63
Rev. 1.90
21
May 17, 2004
A/D Converter
The 8 channels and 8-bit resolution (7-bit accuracy) A/D
converter are implemented in this microcontroller. The
reference voltage is AVDD. The AVDD pin must be con-
nected to VDD externally. Conversion accuracy may
therefore be degraded by voltage drops and noise in the
event of heavily loaded or badly coupled power supply
lines. The A/D converter contains 3 special registers
which are; ADR (21H), ADCR (22H) and ACSR (23H).
The ADR is A/D result register. After the A/D conversion
is completed, the ADR should be read to get the conver-
sion result data. The ADCR is an A/D converter control
register, which defines the A/D channel number, analog
channel select, start A/D conversion control bit and the
end of A/D conversion flag. If the users want to start an
A/D conversion, after select the converted analog chan-
nel, and then give START bit a positive pulse (0
At the end of A/D conversion, the EOCB bit is cleared
and an A/D converter interrupt occurs(if the A/D con-
verter interrupt is enabled). The ACSR is an A/D clock
setting register, which is used to select the A/D clock
source.
1
0).
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of 8
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled. The EOCB
bit (bit 6 of the ADCR) is end of A/D conversion flag.
Check this bit to know when A/D conversion is com-
pleted. The START bit of the ADCR is used to begin the
conversion of A/D converter. Give START bit a falling
edge that means the A/D conversion has started. The
A/D converter remains in reset state while the START
stays at
1
. In order to ensure the A/D conversion is
completed, the START should stay at
0
until the
EOCB is cleared to
0
(end of A/D conversion).
The bit 7 of the ACSR is used for testing purpose only. It
can not be used for the users. The bit1 and bit0 of the
ACSR are used to select A/D clock sources.
When the A/D conversion is completed, the A/D inter-
rupt request flag is set. The bit is set to 1 when the
START bit is set to 1 .
Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADR
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D3
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LCD Bias Block Diagram and Application Circuit
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