參數(shù)資料
型號(hào)： HT46R63
廠商： Holtek Semiconductor Inc.
英文描述： A/D with LCD Type 8-Bit MCU
中文描述： 在A / D液晶型8位微控制器
文件頁(yè)數(shù)： 18/44頁(yè)
文件大小： 328K
代理商： HT46R63
HT46R63/HT46C63
Rev. 1.90
18
May 17, 2004
When the timer/event counter (reading TMRH) is read,
the cl
ock will be blocked to avoid errors. As this may re-
sults in a counting error, this must be taken into consid-
eration by the programmer.
(Label
Function
0~2 Unused bits, read as 0
TE
3
To define the active edge of TMR pin in-
put signal
(0=active on low to high;
1=active on high to low)
TON
4
To enable or disable timer counting
(0=disabled; 1=enabled)
5
Unused bit, read as 0
TM0
TM1
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC Register
Input/Output Ports
There are 32 bi-directional input/output lines in the mi-
cro-controller, labeled from PAto PD, which are mapped
to the data memory of [12H], [14H], [16H] and [18H], re-
spectively. All of these I/O ports can be used as input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction MOV A,[m] (m=12H, 14H,
16H or 18H). For output operation, all the data is latched
and remains unchanged until the output latch is rewrit-
ten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or schmitt trig-
ger input with or without (depends on options) pull-high
resistorstructurescanbereconfigureddynamically(i.e.,
on-the fly) under software control. To function as an in-
put,thecorrespondinglatchofthecontrolregisterhasto
be set as 1 . The pull-high resistor (if the pull-high re-
sistor is enabled) will be exhibited automatically. The in-
putsourcesarealsodependentonthecontrolregister.If
the control register bit is 1 , the input will read the pad
state ( mov and read-modify-write instructions). If the
control register bit is 0 , the contents of the latches will
move to internal data bus ( mov and read-modify-write
instructions). The input paths (pad state or latches) of
read-modify-write instructions are dependent on the
control register bits. For output function, CMOS is the
only configuration. These control registers are mapped
to locations 13H, 15H, 17H and 19H.
After a chip reset, these input/output lines stay at a high
level (pull-high options) or floating state (non-pull-high
options). Each bit of these input/output latches can be
set or cleared by SET [m].i (m=12H, 14H, 16H or 18H)
instructions. Some instructions first input data and then
follow the output operations. For example, SET [m].i
CLR [m].i , CPLA [m] read the entire port states into
theCPU,executethedefinedoperations(bit-operation),
5
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Input/Output Ports
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