參數(shù)資料
型號(hào)： HT46R63
廠商： Holtek Semiconductor Inc.
英文描述： A/D with LCD Type 8-Bit MCU
中文描述： 在A / D液晶型8位微控制器
文件頁(yè)數(shù)： 15/44頁(yè)
文件大小： 328K
代理商： HT46R63
HT46R63/HT46C63
Rev. 1.90
15
May 17, 2004
Once a wake-up event occurs, it takes 1024 t
SYS
(sys-
tem clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
The 32.768kHz crystal oscillator still run or stop in the
halt mode. (decided by option)
Reset
Therearethreewaysinwhicharesetcanoccur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set thatresetsonlythePCandSP,leavingtheothercir-
cuits in their original state. Some registers remain un-
changed during other reset conditions. Most registers
are reset to the initial condition when the reset condi-
tions are met. By examining the PDF and TO flags, the
programcandistinguishbetweendifferent chipresets .
TO PDF
Reset Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: u means unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (system start-up timer) provides an
extra-delay to delay 1024 system clock pulses when
system power-up or the system awakes from the HALT
state.
When the system power-up occurs, the SST delay is
added during the reset period. But when the reset co-
mes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
The chip reset statuses of the functional units are as
shown.
PC
000H
Interrupt
Disable
WDT
Clear. After master reset, WDT
begins counting
Timer/Event Counter Off
Input/Output Ports
Input mode
SP
Points to the top of the stack
#
6
5
& $ 4 ! #
2 & %
$ - $ #
Reset Timing Chart
$ - $ #
7 . *
, 1
$ - $ #
6
> - # $
$ - $ #
4 & #
& % % , $
! " # $
Reset Configuration
6
5
(
(
E
; F
E
; F
Reset Circuit
Note:
* Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
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