- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄385398 > HT36A4 (Holtek Semiconductor Inc.) 8-Bit Music Synthesizer MCU PDF資料下載
參數(shù)資料
| 型號(hào)： | HT36A4 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit Music Synthesizer MCU |
| 中文描述： | 8位微控制器音樂(lè)合成器 |
| 文件頁(yè)數(shù)： | 7/22頁(yè) |
| 文件大?。?/td> | 247K |
| 代理商： | HT36A4 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)
HT36A4
Rev. 1.00
7
July 2, 2003
readinstructionhastobeappliedinboththemainrou-
tine and the ISR, the interrupt should be disabled prior
to the table read instruction. It will not be enabled until
the TBLH has been backed up. All table related in-
structions need 2 cycles to complete the operation.
These areas may function as normal program mem-
ory depending upon user requirements.
Bank pointer
The program memory is organized into 8 banks and
each bank into 8192 16 bits of program ROM. PF[1~0]
is bank pointer. After an instruction has been executed
to write data to the PF register to select a different
bank,notethatthenewbankwillnotbeselectedimme-
diately. It is not until the following instruction has com-
pleted execution that the bank will be actually selected.
It should be note that the PF register has to be cleared
before setting to output mode.
Wavetable ROM
The ST[10~0] is used to defined the start address of
each sample on the wavetable and read the waveform
data from the location. HT36A4 provides 16 output ad-
dress lines from WA[14~0], the ST[10~0] is used to lo-
cate the major 16 bits i.e. WA[14:5] and the undefined
data from WA[4~0] is always set to 00000b. So the start
address of each sample have to be located at a multiple
of 32. Otherwise, the sample will not be read out cor-
rectly because it has a wrong starting code.
Stack Register
Stack
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack.Afterachipreset,theSPwillpointtothetopofthe
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is subse-
quently executed, a stack overflow occurs and the first
entry will be lost (only the most recent eight return ad-
dress are stored).
Data Memory
RAM
The data memory is designed with 256 8 bits. The data
memory is divided into three functional groups: special
function registers, wavetable function register, and gen-
eral purpose data memory (208 8). Most of them are
read/write, but some are read only.
The special function registers include the Indirect Ad-
dressing register 0 (00H), the Memory Pointer register 0
(MP0;01H), the Indirect Addressing register 1 (02H), the
Memory Pointer register 1 (MP1;03H), the Accumulator
(ACC;05H), the Program Counter Lower-byte register
(PCL;06H), the Table Pointer (TBLP;07H), the Table
Higher-order byte register (TBLH;08H), the Watchdog
Timer option Setting register (WDTS;09H), the Status
register (STATUS;0AH), the Interrupt Control register
(INTC;0BH), the Timer Counter 0 Lower-order byte reg-
ister (TMR0L;0DH), the Timer Counter 0 control register
(TMR0C;0EH), the Timer Counter 1 Lower-order byte
register (TMR1L;10H), the Timer Counter 1 Control reg-
ister (TMR1C;11H), the I/O registers (PA;12H) and the
I/O Control registers (PAC;13H). The program ROM
bank select (PF;1CH). The DAC High byte (DAH;1DH).
The DAC low byte (DAL;1EH). The DAC control
(DAC;1FH). The wavetable function registers is defined
between 20H~2AH. The remaining space before the
30H is reserved for future expanded usage and reading
these locations will return the result 00H. The general
purpose data memory, addressed from 30H to FFH, is
used for data and control information under instruction
command.
All data memory areas can handle arithmetic, logic, in-
crement, decrement and rotate operations directly. Ex-
cept for some dedicated bits, each bit in the data
memory can be set and reset by the SET [m].i and CLR
[m].i instructions, respectively. They are also indirectly
accessible through Memory pointer registers
(MP0:01H, MP1:03H).
Instruction(s)
Table Location
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P12
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note:
*12~*0: Bits of table location
P12~P8: Bits of current Program Counter
@7~@0: Bits of table pointer
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HT3810 | 128 NOTE MELODY GENERATORS |
| HT3810A | 128 NOTE MELODY GENERATORS |
| HT3810B | 128 NOTE MELODY GENERATORS |
| HT3810C | 128 NOTE MELODY GENERATORS |
| HT3810D | 128 NOTE MELODY GENERATORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HT36A4_07 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Music Synthesizer 8-Bit MCU |
| HT36ARP | 功能描述:兩端交流開(kāi)關(guān)元件 32-40V RoHS:否 制造商:STMicroelectronics 轉(zhuǎn)折電流 VBO:45 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-23 封裝:Reel |
| HT36B | 功能描述:兩端交流開(kāi)關(guān)元件 34-38V RoHS:否 制造商:STMicroelectronics 轉(zhuǎn)折電流 VBO:45 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-23 封裝:Reel |
| HT-36B | 制造商:TECCOR 制造商全稱:TECCOR 功能描述:Bilateral Trigger Diacs |
| HT36B0 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:8-Bit Music Synthesizer MCU |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。