參數(shù)資料
型號: HT36A4
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit Music Synthesizer MCU
中文描述: 8位微控制器音樂合成器
文件頁數(shù): 6/22頁
文件大?。?/td> 247K
代理商: HT36A4
HT36A4
Rev. 1.00
6
July 2, 2003
Program ROM
HT36A4 provides 15 address lines WA[14:0] to read the
Program ROM which is up to 512 bits, and is commonly
used for the wavetable voice codes and the program
memory. It provides two address types, one type is for
program ROM, which is addressed by a bank pointer
PF1~0 and a 13-bit program counter PC 12~0; and the
other type is for wavetable code, which is addressed by
the start address ST10~0. On the program type,
WA14~0= PF2~0 2
13
+ PC12~0. On the wave table
ROM type, WA14~0=ST10~0 2
5
.
Program Memory
ROM
The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8192 16 bits, addressed by the bank pointer, program
counter and table pointer.
Certain locations in the program memory of each bank
are reserved for special usage:
Location 000H on bank0
This area is reserved for the initialization program. Af-
ter chip reset, the program always begins execution at
location 000H on bank0.
Location 008H
This area is reserved for the Timer Counter 0 interrupt
service program on each bank. If timer interrupt results
from a Timer Counter 0 overflow, and if the interrupt is
enabled and the stack is not full, the program begins ex-
ecution at location 008H corresponding to its bank.
Location 00CH
This area is reserved for the Timer Counter 1 interrupt
service program on each bank. If a timer interrupt re-
sults from a Timer Counter 1 overflow, and if the inter-
rupt is enabled and the stack is not full, the program
begins execution at location 00CH corresponding to
its bank.
Table location
Any location in the ROM space can be used as
look-up tables. The instructions TABRDC [m] (the cur-
rent page, 1 page=256 words) and TABRDL [m] (the
last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
higher-order byte of the table word are transferred to
the TBLH. The Table Higher-order byte register
(TBLH) is read only. The Table Pointer (TBLP) is a
read/write register (07H), which indicates the table lo-
cation. Before accessing the table, the location must
be placed in TBLP. The TBLH is read only and cannot
be restored. If the main routine and the ISR (Interrupt
Service Routine) both employ the table read instruc-
tion, the contents of the TBLH in the main routine are
likely to be changed by the table read instruction used
in the ISR. Errors can occur. In this case, using the ta-
ble read instruction in the main routine and the ISR si-
multaneously should be avoided. However, if the table
Mode
Program Counter
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Timer/EventCounter0Overflow
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/EventCounter1Overflow
0
0
0
0
0
0
0
0
0
1
1
0
0
Skip
PC+2
Loading PCL
*12
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#12
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return From Subroutine
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program counter
Note:
*12~*0: Bits of Program Counter
#12~#0: Bits of Instruction Code
@7~@0: Bits of PCL
@7~@0: Bits of PCL
S12~S0: Bits of Stack Register
2
2
' 8
+
9
+ +
+
; 9
9 <
8
+ ;
= 9 9 4
+
;
+ ) $
+ > 9
,
2
= 9 9 4
+
;
+ ) $
+ > 9
,
. . . 2
( 9
@ + +
<
+ : 9 8 +
+ 9 + . -
. . 2
' 8
+
9
+ +
+
; 9
2
"
A 0
+
3
9
+
9 <
8
Program memory for each bank
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