HT36A4
Rev. 1.00
14
July 2, 2003
Timer 0/1
Timer 0 is an 8-bit counter, and its clock source comes
from the system clock divided by an 8-stage prescaler.
There are one registers related to Timer 0;
TMR0L(0DH) and TMR0C(0EH). One physical registers
are mapped to TMR0L location; writing TMR0L makes
the starting value be placed in the Timer 0 preload regis-
ter and reading the TMR0 gets the contents of the Timer
0 counter. The TMR0C is a control register, which de-
fines the division ration of the prescaler and counting
enable or disable.
Writing data to B2, B1 and B0 (bits 2, 1, 0 of TMR0C)
can yield various clock sources.
One the Timer 0 starts counting, it will count from the
current contents in the counter to FFH. Once an over-
flow occurs, the counter is reloaded from a preload reg-
ister, and generates an interrupt request flag (T0F; bit 2
of INTCH). To enable the counting operation, the timer
On bit (TON; bit 4 of TMR0C) should be set to 1 . For
proper operation, bit 7 of TMR0C should be set to 1
and bit 3, bit 6 should be set to 0 .
There are two registers related to the Timer Counter1;
TMR1L(10H), TMR1C(11H). The Timer Counter 1 oper-
ates in the same manner as Timer Counter 0.
TMR0C/TMR1C
T0F
B2
B1
B0
0
0
0
SYS CLK/16
0
0
1
SYS CLK/32
0
1
0
SYS CLK/64
0
1
1
SYS CLK/128
1
0
0
SYS CLK/256
1
0
1
SYS CLK/512
1
1
0
SYS CLK/1024
1
1
1
SYS CLK/2048
TMR0C Bit 4 to enable/disable timer counting
(1=enable; 0=disable)
TMR0C Bit 3, always write 0 .
TMR0C Bit 5, always write 0 .
TMR0C Bit 6, always write 0 .
TMR0C Bit 7, always write 1 .
Input/Output Ports
There are 8 bidirectional input/output lines labeled PA,
which are mapped to the data memory of [12H] respec-
tively. All these I/O ports can be used for input and out-
put operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction MOV A,[m] (m=12H). For out-
put operation, all data is latched and remains un-
changed until the output latch is rewritten.
Each I/O line has its own control register (PAC) to con-
trol the input/output configuration. With this control reg-
ister, CMOS output or Schmitt trigger input with or
without pull-high resistor (mask option) structures can
be reconfigured dynamically under software control. To
function as an input, the corresponding latch of the con-
trol register must write a 1 . The pull-high resistance
will exhibit automatically if the pull-high option is se-
lected. The input source also depends on the control
register. If the control register bit is 1 , input will read
the pad state. If the control register bit is 0 , the con-
tents of the latches will move to the internal bus. The latter
is possible in read-modify-write instruction. For output
function, CMOS is the only configuration. These control
registers are mapped to locations 13H.
1
8
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Timer 0/1
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Input/output ports