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參數(shù)資料
| 型號： | HSDL-7002 |
| 廠商： | Avago Technologies Ltd. |
| 英文描述： | 3/16 Encode/Decode Integrated Circuit in QFN Package |
| 中文描述： | 3 / 16編碼/解碼電路集成采用QFN封裝 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 243K |
| 代理商： | HSDL-7002 |
4
Recommended Operating Conditions
(Vcc = 2.7 to 5.5 V, T
A
= -20 to +85 °C)
Parameter
Supply Voltage
Input Voltage
Ambient Temperature
High Level Input Voltage
Low Level Input Voltage
Output High Voltage
Notes:
1. IrDA
Parameter. The Max Clk Frequency represents the maximum clock frequency to drive the HSDL-7002’s internal state machine. Under
normal circumstances, the clock input should not exceed 16*115.2 kbit/s or 1.8432 MHz. This product can operate at higher clock rates, but the
above is the recommended rate.
2. The Maximum Pulse Width (t
mpw
) represents the minimum pulse width of the encoded IR_TXD pulse (and the IR_RXD pulse). As per the IrDA
Physical Layer Specification 1.4, the minimum pulse of the IR_TXD and IR_RXD pulses should be 3*(1/1.8432 MHz) or 1.63 μs.
Symbol
V
CC
V
I
T
A
V
IH
V
IL
V
OH
Min.
2.7
0
-20
0.7 V
CC
0
2.6
Typ.
5.0
Max.
5.5
V
CC
+85
V
CC
0.3 V
CC
Units
V
V
°C
V
V
V
Conditions
V
CC
= 2.7 V
I
OH
= 2 mA
V
CC
= 2.7 V
I
OL
= 2 mA
V
CC
= 5.5 V
I
OH
= 2 mA
V
CC
= 2.7 V
I
OL
= 2 mA
Output Low Voltage
V
OL
0.1
V
Output High Voltage
V
OH
5.1
V
Output Low Voltage
V
OL
0.1
V
Static Power Dissipation
Dynamic Power Dissipation
Static Current Consumption
P
STAT
P
DYN
I
STAT
0.61
16.5
50
100
3
3
2
mW
mW
m
A
V
CC
= 2.7 V
V
CC
= 5.5 V
V
CC
= 2.7 V
V
CC
= 5.5 V
Dynamic Current Consumption
I
DYN
1.08
2.45
mA
Max Clk Frequency
(16XCLK)
[1]
Minimum Pulse Width
(IR_TXD)
[2]
Pulse Width on Monoshot
(IR_TXD and IR_RXD)
Value of Pulldown Resistor used on POW-
ERDN & PULSEMOD input pins
Trigger Low Level Input Voltage
(For NRST input pin)
Trigger High Level Input Voltage
(For NRST input pin)
f16XCLK
MHz
tmpw
1628
ns
tmpw
1628
ns
RDWN
400
213
0.93
2.11
1.68
3.22
460
237
0.96
2.14
1.69
3.23
510
260
0.98
2.15
1.70
3.25
kW
V
CC
= 2.7 V
V
CC
= 5.5 V
V
CC
= 2.7 V
V
CC
= 5.5 V
V
CC
= 2.7 V
V
CC
= 5.5 V
VIL_TRIG
V
VIH_TRIG
V
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