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參數(shù)資料
| 型號(hào)： | HSDL-7002 |
| 廠商： | Avago Technologies Ltd. |
| 英文描述： | 3/16 Encode/Decode Integrated Circuit in QFN Package |
| 中文描述： | 3 / 16編碼/解碼電路集成采用QFN封裝 |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 243K |
| 代理商： | HSDL-7002 |
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CRYSTAL
CLK
INT CLK
(DIV BY 2)
TXD
INTERNAL
IRTXD
OUTPUT
IRTXD
(MONOSHOT)
6 CRYSTAL CYCLES
The figure above illustrates the operation of the monoshot
when the internal clock is set to divide by 2 mode, i.e.,
when A2=0, A1=0, and A0=0. A rising edge on the internal
modulation state machine (IR_TXD output), will cause the
output on the IR_TXD to go up for 6 crystal clock cycles.
With a 3.6864 MHz clock, this corresponds to a pulse of
1.63 μs. The duration of this pulse is independent of the
code A2, A1, A0 and is always 6 clock cycles of the crystal,
corresponding to the monoshot operation.
Monoshot Operation
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright 2006 Avago Technologies Limited. All rights reserved. Obsoletes 5989-1319EN
AV02-0683EN - September 5, 2007
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