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參數(shù)資料
| 型號： | HSDL-7002 |
| 廠商： | Avago Technologies Ltd. |
| 英文描述： | 3/16 Encode/Decode Integrated Circuit in QFN Package |
| 中文描述： | 3 / 16編碼/解碼電路集成采用QFN封裝 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 243K |
| 代理商： | HSDL-7002 |
10
Encoding Scheme
The encoding scheme relies on a clock being present,
which is set to 16 times the data transmission baud rate
(16XCLK). The encoder sends a pulse for every space or
“0” that is sent on the TXD line. On a high to low transition
of the TXD line, the generation of the pulse is delayed for
7 clock cycles of the 16XCLK before the pulse is set high
for 3 clock cycles (or 3/16th of a bit time) and then subse-
quently pulled low. This generates a 3/16th
bit time pulse
centered around the bit of information (“0”) that is being
transmitted. For consecutive spaces, pulses with a 1 bit
time delay are generated in series. If a logic “1” (mark) is
sent then the encoder does not generate a pulse.
Figure 7. HSDL-7002 Encoding Scheme
Figure 8. HSDL-7002 Decoding Scheme
Notes:
1. The stretched pulse must be at least of a bit time in duration to be correctly interpreted by a UART.
2. It is recommended that the TXD remains high when not transmitting. This ensures the LED is off and will not interfere with signal
reception.
RXD
IRRXD
16XCLK
16 CYCLES
16 CYCLES
16 CYCLES
16 CYCLES
3 CS
IRTXD
TXD
16XCLK
16 CYCLES
16 CYCLES
16 CYCLES
16 CYCLES
7 CS
3 CS
Decoding Scheme
The IrDA
-SIR decoding modulation method can be
thought of as a pulse-stretching scheme. Every high to
low transition of the IR_RXD line signifies the arrival of a
pulse. This pulse needs to be stretched to accommodate 1
bit time (or 16 16XCLK cycles). Every pulse that is received
is translated into a “0” or space on the RXD line equal to
1 bit time.
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