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參數(shù)資料
| 型號： | HSDL-7002 |
| 廠商： | Avago Technologies Ltd. |
| 英文描述： | 3/16 Encode/Decode Integrated Circuit in QFN Package |
| 中文描述： | 3 / 16編碼/解碼電路集成采用QFN封裝 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 243K |
| 代理商： | HSDL-7002 |
2
Order Information
Figure 2. HSDL-7002 Pin Configuration
Part Number Packaging Type
HSDL-7002
Tape and Reel
Quantity
2500
I/O Pins Configuration Table
Name
1
TXD
Marking Information
The unit is marked with A7002 and ‘yyww’ on the chip.
yy = year
ww = work week
Note:
There are two methods of putting the internal oscillator cell in POWERDOWN MODE. Whenever the CLK_SEL pin is asserted high (external clock
select) the oscillator is automatically put in powerdown mode, or whenever the POWERDN pin asserted high.
Type
Digital In
Function
Negative edge triggered input signal that is normally tied to the SOUT signal
of the UART (serial data to be transmitted). Data is modulated and output as
IR_TXD.
Output signal normally tied to SIN signal of a UART (received serial data).
RXD is the demodulated output of IR_RXD.
Clock Multiplex Signal
Clock Multiplex Signal
Clock Multiplex Signal
Used to activate either the internal or external clock. A high on this line
activated the external clock (16XCLK) and a low activates the internal clock.
When the external clock is activated, the internal oscillator is put in POWERDN
mode.
Chip Ground
Activate low signal used to reset the IrDA
SIR Encode & Decode state ma-
chine. This signal can be tied to POR (Power-On-Reset) or Vcc.
Input from SIR optoelectronics. Input signal is a 3/16th or 1.63 ms pulse that is
demodulated to generate RXD output signal.
This is the modulated TXD signal.
A high level on this input put the chip into the monoshot transmit mode. In
this mode, when there is a negative transition on the TXD input, a rising edge
on the internal transmit modulation state machine will activate a high pulse
on IR_TXD for 6 crystal clock cycles. With a 3.6864 MHz crystal, this corre-
sponds to 1.63 ms. This mode cannot be used in conjunction with the 16XCLK
clock. It is meant to be used with the external crystal clock. By default, this
input pin is pulled to GND
A high on this input put only the internal oscillator cell in POWERDN mode.
The cell is normally not powered down.
Oscillator Output
Oscillator Input
Power
Positive edge triggered input clock that is set to 16 times the data transmis-
sion baud rate. The encode and decode schemes require this signal. The signal
is usually tied to a UART’s BAUDOUT signal. The 16XCLK may be provided by
application circuitry if BAUDOUT is not available. This signal is required when
the internal clock is not used.
2
RXD
Digital Out
3
4
5
6
A0
A1
A2
CLK_SEL
Digital In
Digital In
Digital In
Digital In
7
8
GND
NRST
Digital In
9
IR_RXD
Digital In
10
11
IR_TXD
PULSEMOD Digital In
Digital Out
(with pull down)
12
POWERDN
Digital In
(with pull down)
Analog Out
Analog In
13
14
15
16
OSCOUT
OSCIN
Vcc
16XCLK
Digital In
PIN #1
CORNER
P
Pin 12
Pin 11
Pin 10
Pin 9
Pin 4
Pin 3
Pin 2
Pin 1
P
P
P
P
P
P
P
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