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參數(shù)資料
| 型號(hào)： | HS1-82C55ARH-8 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | Radiation Hardened CMOS Programmable Peripheral Interface |
| 中文描述： | 24 I/O, PIA-GENERAL PURPOSE, CDIP40 |
| 文件頁(yè)數(shù)： | 14/23頁(yè) |
| 文件大?。?/td> | 165K |
| 代理商： | HS1-82C55ARH-8 |
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HS-82C55ARH
The mode definitions and possible mode combinations may
seem confusing at first but after a cursory review of the
complete device operation a simple, logical I/O approach will
surface. The design of the HS-82C55ARH has taken into
account things such as efficient PC board layout, control
signal definition vs PC layout and complete functional
flexibility to support almost any peripheral device with no
external logic. Such design represents the maximum use of
the available pins.
FIGURE 12. BIT SET/RESET CONTROL WORD FORMAT
Single Bit/Set/Reset Feature
Any of the eight bits of Port C can be Set or Reset using a
single OUTput instruction. See Figure 12. This feature
reduces
software
requirements
applications.
in
control-based
D7 D6 D5 D4 D3 D2 D1 D0
CONTROL WORD
BIT SET/RESET
1 = SET
0 = RESET
BIT SELECT
0
0
0
0
0
1
1
0
2
0
1
0
3
1
1
0
4
0
0
1
5
1
0
1
6
0
1
1
7
1
1
1
B0
B1
B2
BIT SET/RESET FLAG
0 = ACTIVE
DON’T
CARE
X
X
X
Interrupt Control Functions
When the HS-82C55ARH is programmed to operate in
Mode 1 or Mode 2, control signals are provided that can be
used as interrupt request inputs to the CPU. The interrupt
request signals, generated from Port C, can be inhibited or
enable by setting or resetting the associated INTE flip-flop,
using the Bit Set/Reset function of Port C.
This function allows the programmer to enable or disable a
CPU interrupt by a specific I/O device without affecting any
other device in the interrupt structure.
INTE Flip-Flop Definition:
(BIT-SET) - INTE is SET - Interrupt enable.
(BIT-RESET) - INTE is RESET - Interrupt disable.
NOTE: All mask flip-flops are automatically reset during
mode selection and device Reset.
Operating Modes
Mode 0 (Basic Input/Output)
This functional configuration provides simple input and out-
put operations for each of the three ports. No handshaking it
required, data is simply written to or read from a specific
port.
Mode 0 Basic Functional Definitions:
Two 8-bit ports and two 4-bit ports
Any port can be input or output
Outputs are latched
Inputs are not latched
16 different Input/Output configurations possible
FIGURE 13. MODE 0 (BASIC INPUT)
FIGURE 14. MODE 0 (BASIC OUTPUT)
TRLRH
TPVRL
TRHPX
TAVRL
TRHAX
TRLDV
TRHDX
RD
INPUT
CS, A1, A0
D7 - D0
WR
D7 - D0
CS, A1, A0
OUTPUT
TWLWH
TDVWH
TWHDX
TAVWL
TWHAX
TWHPV
Spec Number
518060
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HS1-82C55ARH-Q | 制造商:Intersil Corporation 功能描述:PERIPHERAL INTRFC 40CDIP - Rail/Tube |
| HS1-82C59ARH-8 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Interrupt Controller |
| HS1-82C85RH | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Radiation Hardened CMOS Static Clock Controller/Generator |
| HS1-82C85RH-8 | 制造商:Intersil Corporation 功能描述:CLOCK CNTRLR/GENERATOR 24PIN SBDIP - Rail/Tube |
| HS1-82C85RH-Q | 制造商:Intersil Corporation 功能描述:CLOCK CNTRLR/GENERATOR 24PIN SBDIP - Rail/Tube |
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