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參數(shù)資料
| 型號： | HS1-82C55ARH-8 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Radiation Hardened CMOS Programmable Peripheral Interface |
| 中文描述： | 24 I/O, PIA-GENERAL PURPOSE, CDIP40 |
| 文件頁數(shù)： | 12/23頁 |
| 文件大?。?/td> | 165K |
| 代理商： | HS1-82C55ARH-8 |
981
HS-82C55ARH
Functional Description
The HS-82C55ARH is a programmable peripheral interface
designed to allow microcomputer systems to control and
interface with all types of peripheral devices.It has the
ability to generate and respond to all asynchronous hand-
shaking signals necessary to transfer data to and from
peripheral devices, and it can also interrupt the processor
when a peripheral needs servicing. These capabilities allow
the HS-82C55ARH to be used in an unlimited number of
applications including EXTERNAL SYSTEM CONTROL,
ASYNCHRONOUS DATA TRANSFER, and SYSTEMS
MONITORING.
Data Bus Buffer
This tri-state bidirectional 8-bit buffer is used to interface the
HS-82C55ARH to the system data bus (see Figure 8). Data
is transmitted or received by the buffer upon execution of
input or output instructions by the CPU. Control words and
status information are also transferred through the data bus
buffer.
FIGURE 8. BLOCK DIAGRAM DATA BUS BUFFER, READ/WRITE,
GROUP A AND B CONTROL LOGIC FUNCTIONS
Read/Write and Control Logic
The function of this block is to manage all of the internal and
external transfer of both Data and Control or Status words. It
accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control Groups.
Group A and Group B Controls
The functional configuration of each port is programmed by
the systems software. In essence, the CPU writes a control
word to the HS-82C55ARH. The control word contains infor-
mation such as “mode”, “bit set”, “bit reset”, etc., that initial-
izes the functional configuration of the HS-82C55ARH.
Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control Logic, receives
“control words” from the internal data bus and issues the
proper commands to its associated ports.
Control Group - Port A and Port C upper (C7 - C4)
Control Group - Port B and Port C lower (C3 - C0).
GROUP
A
CONTROL
POWER
SUPPLIES
BUS
BUFFER
GROUP
B
CONTROL
READ/
WRITE
CONTROL
LOGIC
RD
WR
A1
A0
RESET
CS
D7-
D0
BIDIRECTIONAL
DATA BUS
+5V
GND
8-BIT INTERNAL
DATA BUS
GROUP
BB (8)
GROUP
(4)
G(4)
GROUP
A (8)
I/O
PA0
I/O
PC4
I/O
PC0
I/O
PB0
Ports A, B, C
The HS-82C55ARH contains three 8-bit ports (A, B and C).
All can be configured to a wide variety of functional
characteristics by the system software but each has its own
special features or “personality” to further enhance the
power and flexibility of the HS-82C55ARH.
Port A
One 8-bit data output latch/buffer and one 8-bit data
input latch. Both “pull-up” and “pull-down” bus hold
devices are present on Port A. See Figure 9A.
Port B
One 8-bit data input/output latch/buffer and one 8-
bit data input buffer. See Figure 9B.
Port C
One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be
divided into two 4-bit ports under the mode control.
Each 4-bit port contains a 4-bit latch and can be used
for the control signal outputs and status signal inputs
in conjunction with Ports A and B. See Figure 9B.
(A)
(B)
FIGURE 9. I/O PORT CONFIGURATION
Operational Description
Control Word
The data direction and mode of Ports A, B and C are
determined by the contents of the Control Word. See Figure
11. The Control Word can be both written and read as shown
in Table 1 and 2. During write operations, the function of the
Control Word being written is determined by data bit D7. If
D7 is low, the data on D0 - D3 will set or reset one of the bits
of Port C. See Figure 12. During read Operations, the
MASTER
RESET
INTERNAL
DATA IN
INTERNAL
DATA OUT
WR
SIGNAL
RD
CONTROL
EXTERNAL
PORT A PIN
MASTER
RESET
INTERNAL
DATA IN
INTERNAL
DATA OUT
WR
SIGNAL
EXTERNAL
PORT B, C
PIN
P
VDD
Spec Number
518060
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