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參數(shù)資料
| 型號： | HS1-65647RH |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | DRAM |
| 英文描述： | Radiation Hardened 8K x 8 SOS CMOS Static RAM |
| 中文描述： | 8K X 8 STANDARD SRAM, 50 ns, CDIP28 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 110K |
| 代理商： | HS1-65647RH |
838
HS-65647RH
Spec Number
518729
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric mate-
rials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-
der dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
-D-
-C-
0.004
H A - B
M
D
S
S
-A-
-B-
0.036
H A - B
M
D
S
S
e
E
A
Q
L
D
A
A
E1
SEATING AND
BASE PLANE
L
E2
E3
E3
-H-
b
C
S1
M
c1
b1
(c)
(b)
SECTION A-A
BASE
METAL
LEAD FINISH
PIN NO. 1
ID AREA
M
K36.A
36 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.138
-
3.51
-
b
0.006
0.013
0.15
0.33
-
b1
0.006
0.010
0.15
0.25
-
c
0.004
0.011
0.10
0.28
-
c1
0.004
0.008
0.10
0.20
-
D
0.620
0.640
15.75
16.26
3
E
0.620
0.640
15.75
8.64
-
E1
-
0.660
-
16.76
3
E2
0.470
0.490
11.94
12.45
-
E3
0.030
-
0.76
-
7
e
0.025 BSC
0.64 BSC
-
k
-
-
-
-
-
L
0.240
0.280
6.10
7.11
-
Q
0.026
0.045
0.66
1.14
8
S1
-
-
-
-
-
M
-
0.0015
-
0.04
-
N
36
36
-
Rev. 0 5/18/94
Packaging
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HS9-65647RH | Radiation Hardened 8K x 8 SOS CMOS Static RAM |
| HS9A-65647RH-Q | Radiation Hardened 8K x 8 SOS CMOS Static RAM |
| HS1-65647RH-Q | Radiation Hardened 8K x 8 SOS CMOS Static RAM |
| HS9-65647RH-Q | Radiation Hardened 8K x 8 SOS CMOS Static RAM |
| HS1-82C52RH-8 | UART |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HS1-65647RH/PROTO | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened 8K x 8 SOS CMOS Static RAM |
| HS1-65647RH-8 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened 8K x 8 SOS CMOS Static RAM |
| HS1-65647RH-Q | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened 8K x 8 SOS CMOS Static RAM |
| HS1-6564RH-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Synchronous SRAM Module |
| HS16-5N | 功能描述:旋鈕開關(guān) 12 AMP 5P 2-11 POS RoHS:否 制造商:C&K Components 位置數(shù)量:5 卡片組數(shù)量: 每卡片組極數(shù):2 電流額定值:250 mA 電壓額定值:125 V 指數(shù)角: 觸點類型: 觸點形式:DPST 端接類型:Solder 安裝類型:Panel 觸點電鍍:Silver |
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